AutIS: Artificial Intelligent Based Automated Interviewing System. - Rupesh Kumar Dewang; Arpit Gupta; Anisha Kumari; Ritik Raj; Akanksha Gupta; Raj Nath Shah; Tanmay Jaiswal; Arvind Mewada (HIS, 2021)

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. - Dinesh Kushwaha; Aditya Sharma; Neha Gupta; Ritik Raj; Ashish Joshi; Jwalant Mishra; Rajat Kohli; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (ISCAS, 2022)

Manticore: Hardware-Accelerated RTL Simulation with Static Bulk-Synchronous Parallelism. - Mahyar Emami; Sahand Kashani; Keisuke Kamahori; Mohammad Sepehr Pourghannad; Ritik Raj; James R. Larus (ASPLOS (4), 2023)

A 475 MHz Manycore FPGA Accelerator for RTL Simulation. - Sahand Kashani; Mahyar Emami; Keisuke Kamahori; Mohammad Sepehr Pourghannad; Ritik Raj; James R. Larus (FPGA, 2024)

Towards Cognitive AI Systems: Workload and Characterization of Neuro-Symbolic AI. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Chaojian Li; Haoran You; Yonggan Fu; Cheng Wan 005; Ananda Samajdar; Yingyan Celine Lin; Tushar Krishna; Arijit Raychowdhury (ISPASS, 2024)

A Secure Blockchain driven Food Supply Chain Prototype for Developing Territory in Farming Zone. - Harsh Kumar; Utkarsh Bharati; Ritik Raj; Hrudaya Kumar Tripathy (SNSFAIT, 2024)

Demystifying Platform Requirements for Diverse LLM Inference Use Cases. - Abhimanyu Bambhaniya; Ritik Raj; Geonhwa Jeong; Souvik Kundu 009; Sudarshan Srinivasan; Midhilesh Elavazhagan; Madhu Kumar; Tushar Krishna (CoRR, 2024)

Towards Efficient Neuro-Symbolic AI: From Workload Characterization to Hardware Architecture. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Chaojian Li; Haoran You; Yonggan Fu; Cheng Wan 005; Sixu Li; Youbin Kim; Ananda Samajdar; Yingyan Celine Lin; et al. (CoRR, 2024)

Axon: A Novel Systolic Array Architecture for Improved Run Time and Energy Efficient GeMM and Conv Operation with On-Chip im2col. - Md Mizanur Rahaman Nayan; Ritik Raj; Shaik Gouse Basha; Tushar Krishna; Azad J. Naeemi (DATE, 2025)

CogSys: Efficient and Scalable Neurosymbolic Cognition System via Algorithm-Hardware Co-Design. - Zishen Wan; Hanchen Yang; Ritik Raj; Che-Kai Liu; Ananda Samajdar; Arijit Raychowdhury; Tushar Krishna (HPCA, 2025)

Efficient Processing of Neuro-Symbolic AI: A Tutorial and Cross-Layer Co-Design Case Study. - Zishen Wan; Che-Kai Liu; Hanchen Yang; Ritik Raj; Arijit Raychowdhury; Tushar Krishna (NeuS, 2025)

SCALE-Sim v3: A modular cycle-accurate systolic accelerator simulator for end-to-end system analysis. - Ritik Raj; Sarbartha Banerjee; Nikhil Chandra; Zishen Wan; Jianming Tong; Ananda Samajdhar; Tushar Krishna (CoRR, 2025)

NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AI. - Hanchen Yang; Zishen Wan; Ritik Raj; Joongun Park; Ziwei Li; Ananda Samajdar; Arijit Raychowdhury; Tushar Krishna (CoRR, 2025)

MCMComm: Hardware-Software Co-Optimization for End-to-End Communication in Multi-Chip-Modules. - Ritik Raj; Shengjie Lin; William Won; Tushar Krishna (CoRR, 2025)

OneDSE: A Unified Microprocessor Metric Prediction and Design Space Exploration Framework. - Ritik Raj; Akshat Ramachandran; Jeff Nye; Shashank Nemawarkar; Tushar Krishna (CoRR, 2025)