Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder. - Rituparna Choudhury; P. Rangababu 001 (VDAT, 2017)

FPGA Implementation of Low Complexity Hybrid Decision Tree Training Accelerator. - Rituparna Choudhury; Shaik Rafi Ahamed; Prithwijit Guha (MWSCAS, 2021)

Training Accelerator for Two Means Decision Tree. - Rituparna Choudhury; Shaik Rafi Ahamed; Prithwijit Guha (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Efficient Hardware Implementation of Decision Tree Training Accelerator. - Rituparna Choudhury; Shaik Rafi Ahamed; Prithwijit Guha (SN Comput. Sci., 2021)

Hardware Implementation of Low Complexity High-speed Perceptron Block. - Rituparna Choudhury; Shaik Rafi Ahamed; Prithwijit Guha (ISCAS, 2022)

FPGA Implementation of Batch-Mode Depth-Pipelined Two Means Decision Tree. - Rituparna Choudhury; Shaik Rafi Ahamed; Prithwijit Guha (IEEE Embed. Syst. Lett., 2023)

Simplified Oblique Decision Tree Accelerator. - Rituparna Choudhury; Shaik Rafi Ahamed; Prithwijit Guha (IEEE Embed. Syst. Lett., 2025)