Charge Scavenging Gate Coupled Hierarchical Bitline Scheme for Ultra-Low Power SRAMs in 65nm LSTP CMOS. - Mukesh Kumar Srivastav; Rimjhim; Govind Soni; Umang Mittal; Rupali Tewari; Riya Yadav; Anuj Grover; Kedar Janardan Dhori; Harsh Rawat (ICECS, 2021)

DRL-Based Transmission Design for Distributed STAR-RIS-aided Communications. - Riya Yadav; Sravani Kurma; Sandeep Kumar Singh 005; Chih-Peng Li; Mayur Parate (ANTS, 2023)

Artificial Intelligence Based Autonomous Traffic Regulator. - Sreelatha R; Mahalakshmi B. S; Riya Yadav; Shreyam Pandey; Vandit Agarwal (SCCTT, 2023)