Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors. - Po-Hao Wang; Shang-Jen Tsai; Rizal Tanjung; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (Integr., 2016)

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures. - Po-Hao Wang; Yung-Chen Chien; Shang-Jen Tsai; Xuan-Yu Lin; Rizal Tanjung; Yi-Sian Lin; Shu-Wei Syu; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)