Case study of a VLSI design project: A simple inner product machine. - Rob A. Rutenbar; Y. E. Park (IEEE Symposium on Computer Arithmetic, 1981)

Cellular image processing techniques for VLSI circuit layout validation and routing. - Trevor N. Mudge; Rob A. Rutenbar; Robert M. Lougheed; Daniel E. Atkins (DAC, 1982)

A Class of Cellular Architectures to Support Physical Design Automation. - Rob A. Rutenbar; Trevor N. Mudge; Daniel E. Atkins (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984)

A Class of Cellular Computer Architectures to Support Physical Design Automation (Vlsi Layout, Integrated Circuit, Routing). - Rob A. Rutenbar (1984)

Future directions for DA machine research (panel session). - Rob A. Rutenbar (DAC, 1985)

Multiprocessor-based placement by simulated annealing. - Saul A. Kravitz; Rob A. Rutenbar (DAC, 1986)

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis. - Ramesh Harjani; Rob A. Rutenbar; L. Richard Carley (DAC, 1987)

A Scanline Data Structure Processor for VLSI Geometry Checking. - Erik C. Carlson; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Placement by Simulated Annealing on a Multiprocessor. - Saul A. Kravitz; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

Mask Verification on the Connection Machine. - Erik C. Carlson; Rob A. Rutenbar (DAC, 1988)

Automatic layout of custom analog cells in ANAGRAM. - David J. Garrod; Rob A. Rutenbar; L. Richard Carley (ICCAD, 1988)

Analog circuit synthesis for performance in OASYS. - Ramesh Harjani; Rob A. Rutenbar; L. Richard Carley (ICCAD, 1988)

Analog circuit synthesis and exploration in OASYS. - Ramesh Harjani; Rob A. Rutenbar; L. Richard Carley (ICCD, 1988)

Systolic routing hardware: performance evaluation and optimization. - Rob A. Rutenbar; Daniel E. Atkins (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software. - Dorothy E. Setliff; Rob A. Rutenbar (DAC, 1989)

Zen and the Art of Analog Design Automation. - Rob A. Rutenbar (IFIP Congress, 1989)

Logic Simulation on Massively Parallel Architectures. - Saul A. Kravitz; Randal E. Bryant; Rob A. Rutenbar (ISCA, 1989)

OASYS: a framework for analog circuit synthesis. - Ramesh Harjani; Rob A. Rutenbar; L. Richard Carley (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW. - Erik C. Carlson; Rob A. Rutenbar (DAC, 1990)

Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II. - John M. Cohn; David J. Garrod; Rob A. Rutenbar; L. Richard Carley (ICCAD, 1991)

A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. - Rajeev Jayaraman; Rob A. Rutenbar (ICCAD, 1991)

Massively parallel switch-level simulation: a feasibility study. - Saul A. Kravitz; Randal E. Bryant; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF. - Dorothy E. Setliff; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

KOAN/ANAGRAM II: new tools for device-level analog placement and routing. - John M. Cohn; David J. Garrod; Rob A. Rutenbar; L. Richard Carley (IEEE J. Solid State Circuits, 1991)

A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis. - Prabir C. Maulik; L. Richard Carley; Rob A. Rutenbar (DAC, 1992)

System-level routing of mixed-signal ASICs in WREN. - Sujoy Mitra; Sudip Nag; Rob A. Rutenbar; L. Richard Carley (ICCAD, 1992)

Knowledge Representation and Reasoning in a Software Synthesis Architecture. - Dorothy E. Setliff; Rob A. Rutenbar (IEEE Trans. Software Eng., 1992)

Latchup-aware placement and parasitic-bounded routing of custom analog cells. - Bülent Basaran; Rob A. Rutenbar; L. Richard Carley (ICCAD, 1993)

Performance-Driven Simultaneous Place and Route for Row-Based FPGAs. - Sudip Nag; Rob A. Rutenbar (DAC, 1994)

ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits. - Emil S. Ochotta; Rob A. Rutenbar; L. Richard Carley (DAC, 1994)

Synthesis of manufacturable analog circuits. - Tamal Mukherjee; L. Richard Carley; Rob A. Rutenbar (ICCAD, 1994)

Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis. - Balsha R. Stanisic; Nishath K. Verghese; Rob A. Rutenbar; L. Richard Carley; David J. Allstot (IEEE J. Solid State Circuits, 1994)

Performance-driven simultaneous place and route for island-style FPGAs. - Sudip K. Nag; Rob A. Rutenbar (ICCAD, 1995)

Testability-oriented channel routing. - Jitendra Khare; Sujoy Mitra; Pranab K. Nag; U. Maly; Rob A. Rutenbar (VLSI Design, 1995)

Reengineering the curriculum: design and analysis of a new undergraduate Electrical and Computer Engineering degree at Carnegie Mellon University. - Stephen W. Director; Pradeep K. Khosla; Ronald A. Rohrer; Rob A. Rutenbar (Proc. IEEE, 1995)

Integer programming based topology selection of cell-level analog circuits. - Prabir C. Maulik; L. Richard Carley; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Substrate-aware mixed-signal macrocell placement in WRIGHT. - Sujoy Mitra; Rob A. Rutenbar; L. Richard Carley; David J. Allstot (IEEE J. Solid State Circuits, 1995)

Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization. - Balsha R. Stanisic; Rob A. Rutenbar; L. Richard Carley (IEEE J. Solid State Circuits, 1995)

An O(n) Algorithm for Transistor Stacking with Performance Constraints. - Bülent Basaran; Rob A. Rutenbar (DAC, 1996)

Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies. - L. Richard Carley; Georges G. E. Gielen; Rob A. Rutenbar; Willy M. C. Sansen (DAC, 1996)

Synthesis of high-performance analog circuits in ASTRX/OBLX. - Emil S. Ochotta; Rob A. Rutenbar; L. Richard Carley (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A hierarchical decomposition methodology for multistage clock circuits. - Gary Ellis; Lawrence T. Pileggi; Rob A. Rutenbar (ICCAD, 1997)

Performance-driven simultaneous placement and routing for FPGA's. - Sudip Nag; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

FPGA routing and routability estimation via Boolean satisfiability. - R. Glenn Wood; Rob A. Rutenbar (IEEE Trans. Very Large Scale Integr. Syst., 1998)

ANACONDA: robust synthesis of analog circuits via stochastic pattern search. - Rodney Phelps; Michael Krasnicki; Rob A. Rutenbar; L. Richard Carley; James R. Hellums (CICC, 1999)

MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells. - Michael Krasnicki; Rodney Phelps; Rob A. Rutenbar; L. Richard Carley (DAC, 1999)

Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT. - Gi-Joon Nam; Karem A. Sakallah; Rob A. Rutenbar (FPGA, 1999)

Inverse polarity techniques for high-speed/low-power multipliers. - Pascal C. H. Meier; Rob A. Rutenbar; L. Richard Carley (ISLPED, 1999)

Satisfiability-Based Detailed FPGA Routing. - Gi-Joon Nam; Karem A. Sakallah; Rob A. Rutenbar (VLSI Design, 1999)

Device-level early floorplanning algorithms for RF circuits. - Mehmet Aktuna; Rob A. Rutenbar; L. Richard Carley (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Case studies: Chip design on the bleeding edge (panel session abstract). - John M. Cohn; Rob A. Rutenbar; Steve J. Young; Chris Malachowsky; Luis Aldaz (DAC, 2000)

Survival strategies for mixed-signal systems-on-chip (panel session). - Stephan Ohr; Rob A. Rutenbar; Henry Chang; Georges G. E. Gielen; Rudolf Koch; Roy McGuffin; K. C. Murphy (DAC, 2000)

A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC. - Rodney Phelps; Michael Krasnicki; Rob A. Rutenbar; L. Richard Carley; James R. Hellums (DAC, 2000)

Life at the end of CMOS scaling (and beyond) (panel session) (abstract only). - Rob A. Rutenbar; Cheming Hu; Mark Horowitz; Stephen Y. Chow (DAC, 2000)

Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution. - Rony Kay; Rob A. Rutenbar (ISPD, 2000)

Layout tools for analog ICs and mixed-signal SoCs: a survey. - Rob A. Rutenbar; John M. Cohn (ISPD, 2000)

Computer-aided design of analog and mixed-signal integrated circuits. - Georges G. E. Gielen; Rob A. Rutenbar (Proc. IEEE, 2000)

Efficient handling of operating range and manufacturing linevariations in analog cell synthesis. - Tamal Mukherjee; L. Richard Carley; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search. - Rodney Phelps; Michael Krasnicki; Rob A. Rutenbar; L. Richard Carley; James R. Hellums (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Reducing power by optimizing the necessary precision/range of floating-point arithmetic. - J. Y. F. Tong; David Nagle; Rob A. Rutenbar (IEEE Trans. Very Large Scale Integr. Syst., 2000)

Panel: (When) Will FPGAs Kill ASICs? - Rob A. Rutenbar; Max Baron; Thomas Daniel; Rajeev Jayaraman; Zvi Or-Bach; Jonathan Rose; Carl Sechen (DAC, 2001)

A boolean satisfiability-based incremental rerouting approach with application to FPGAs. - Gi-Joon Nam; Karem A. Sakallah; Rob A. Rutenbar (DATE, 2001)

Synthesis for Industrial-Scale Analog Intellectual Property. - Rob A. Rutenbar (Evolvable Hardware, 2001)

Direct Transistor-Level Layout for Digital Blocks. - Prakash Gopalakrishnan; Rob A. Rutenbar (ICCAD, 2001)

ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits. - Michael Krasnicki; Rodney Phelps; James R. Hellums; Mark McClung; Rob A. Rutenbar; L. Richard Carley (ICCAD, 2001)

Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design. - Domine Leenaerts; Rob A. Rutenbar; Georges G. E. Gielen (ICCAD, 2001)

Automatic Hierarchical Design: Fantasy or Reality? (Panel). - Rob A. Rutenbar; Olivier Coudert; Patrick Groeneveld; Jürgen Koehl; Scott Peterson; Vivek Raghavan; Naresh Soni (ICCAD, 2001)

Low-power technology mapping for mixed-swing logic. - Rob A. Rutenbar; L. Richard Carley; Roberto Zafalon; Nicola Dragone (ISLPED, 2001)

Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution. - Rony Kay; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Remembrance of circuits past: macromodeling by data mining in large analog design spaces. - Hongzhou Liu; Amith Singhee; Rob A. Rutenbar; L. Richard Carley (DAC, 2002)

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search. - Gi-Joon Nam; Karem A. Sakallah; Rob A. Rutenbar (FPL, 2002)

Floating-point bit-width optimization for low-power signal processing applications. - Claire Fang Fang; Tsuhan Chen; Rob A. Rutenbar (ICASSP, 2002)

Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform. - Claire Fang Fang; Tsuhan Chen; Rob A. Rutenbar (EURASIP J. Adv. Signal Process., 2002)

A new FPGA detailed routing approach via search-based Booleansatisfiability. - Gi-Joon Nam; Karem A. Sakallah; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling. - Claire Fang Fang; Rob A. Rutenbar; Markus Püschel; Tsuhan Chen (DAC, 2003)

Mixed signals on mixed-signal: the right next technology. - Rob A. Rutenbar; David L. Harame; Kurt Johnson; Paul Kempf; Teresa H. Meng; Reza Rofougaran; James Spoto (DAC, 2003)

Floating-point error analysis based on affine arithmetic. - Claire Fang Fang; Tsuhan Chen; Rob A. Rutenbar (ICASSP (2), 2003)

Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs. - Claire Fang Fang; Rob A. Rutenbar; Tsuhan Chen (ICCAD, 2003)

sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing. - Hui Xu 001; Rob A. Rutenbar; Karem A. Sakallah (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Will Moore's Law rule in the land of analog? - Rob A. Rutenbar; Anthony R. Bonaccio; Teresa H. Meng; Ernesto Perea; Robert Pitts; Charles G. Sodini; Jim Wieser (DAC, 2004)

Large-scale placement by grid-warping. - Zhong Xiu; James D. Z. Ma; Suzanne M. Fowler; Rob A. Rutenbar (DAC, 2004)

A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits. - Gang Zhang; E. Aykut Dengi; Ronald A. Rohrer; Rob A. Rutenbar; L. Richard Carley (DAC, 2004)

Towards formal verification of analog designs. - Smriti Gupta; Bruce H. Krogh; Rob A. Rutenbar (ICCAD, 2004)

Static statistical timing analysis for latch-based pipeline designs. - Rob A. Rutenbar; Li-C. Wang; Kwang-Ting Cheng; Sandip Kundu (ICCAD, 2004)

A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints. - Gi-Joon Nam; Fadi A. Aloul; Karem A. Sakallah; Rob A. Rutenbar (IEEE Trans. Computers, 2004)

Scalable trajectory methods for on-demand analog macromodel extraction. - Saurabh K. Tiwary; Rob A. Rutenbar (DAC, 2005)

Timing-driven placement by grid-warping. - Zhong Xiu; Rob A. Rutenbar (DAC, 2005)

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. - Yu-Tsun Chien; Dong Chen; Jea-Hong Lou; Gin-Kou Ma; Rob A. Rutenbar; Tamal Mukherjee (DATE, 2005)

Interval-valued statistical modeling of oxide chemical-mechanical polishing. - James D. Ma; Claire Fang Fang; Rob A. Rutenbar; Xiaolin Xie; Duane S. Boning (ICCAD, 2005)

Fast interval-valued statistical interconnect modeling and reduction. - James D. Z. Ma; Rob A. Rutenbar (ISPD, 2005)

Early research experience with OpenAccess gear: an open source development environment for physical design. - Zhong Xiu; David A. Papa; Philip Chong; Christoph Albrecht; Andreas Kuehlmann; Rob A. Rutenbar; Igor L. Markov (ISPD, 2005)

Time Domain Verification of Oscillator Circuit Properties. - Goran Frehse; Bruce H. Krogh; Rob A. Rutenbar; Oded Maler (FAC, 2005)

On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels. - Saurabh K. Tiwary; Rob A. Rutenbar (CICC, 2006)

Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration. - Saurabh K. Tiwary; Pragati K. Tiwary; Rob A. Rutenbar (DAC, 2006)

Verifying analog oscillator circuits using forward/backward abstraction refinement. - Goran Frehse; Bruce H. Krogh; Rob A. Rutenbar (DATE, 2006)

In silico vox: Towards speech recognition in silicon. - Edward C. Lin; Kai Yu; Rob A. Rutenbar; Tsuhan Chen (Hot Chips Symposium, 2006)

Design automation for analog: the next generation of tool challenges. - Rob A. Rutenbar (ICCAD, 2006)

Faster, parametric trajectory-based macromodels via localized linear reductions. - Saurabh K. Tiwary; Rob A. Rutenbar (ICCAD, 2006)

Moving speech recognition from software to silicon: the in silico vox project. - Edward C. Lin; Kai Yu; Rob A. Rutenbar; Tsuhan Chen (INTERSPEECH, 2006)

Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance. - James D. Ma; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains. - Rob A. Rutenbar (ASP-DAC, 2007)

Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting. - Amith Singhee; Rob A. Rutenbar (DAC, 2007)

Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application. - Amith Singhee; Rob A. Rutenbar (DATE, 2007)

Statistical modeling for the minimum standby supply voltage of a full SRAM array. - Jiajing Wang; Amith Singhee; Rob A. Rutenbar; Benton H. Calhoun (ESSCIRC, 2007)

A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA. - Edward C. Lin; Kai Yu; Rob A. Rutenbar; Tsuhan Chen (FPGA, 2007)

Generating small, accurate acoustic models with a modified Bayesian information criterion. - Kai Yu; Rob A. Rutenbar (INTERSPEECH, 2007)

Mixed-size placement with fixed macrocells using grid-warping. - Zhong Xiu; Rob A. Rutenbar (ISPD, 2007)

From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis. - Amith Singhee; Rob A. Rutenbar (ISQED, 2007)

Collaborative VLSI-CAD Instruction in the Digital Sandbox. - Alex K. Jones; Steven P. Levitan; Rob A. Rutenbar; Yuan Xie 001 (MSE, 2007)

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs. - Rob A. Rutenbar; Georges G. E. Gielen; Jaijeet S. Roychowdhury (Proc. IEEE, 2007)

Interval-Valued Reduced-Order Statistical Interconnect Modeling. - James D. Ma; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Verifying really complex systems: on earth and beyond. - Andreas Kuehlmann; Anjan Bose; David E. Corman; Rob A. Rutenbar; Robert M. Manning; Anna Newman (DAC, 2008)

Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing. - Amith Singhee; Sonia Singhal; Rob A. Rutenbar (DATE, 2008)

Practical, fast Monte Carlo statistical static timing analysis: why and how. - Amith Singhee; Sonia Singhal; Rob A. Rutenbar (ICCAD, 2008)

A low-power hardware search architecture for speech recognition. - Patrick J. Bourke; Rob A. Rutenbar (INTERSPEECH, 2008)

Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design. - Amith Singhee; Jiajing Wang; Benton H. Calhoun; Rob A. Rutenbar (VLSI Design, 2008)

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS. - Benton H. Calhoun; Yu Cao 001; Xin Li 001; Ken Mai; Lawrence T. Pileggi; Rob A. Rutenbar; Kenneth L. Shepard (Proc. IEEE, 2008)

Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools. - Amith Singhee; Claire Fang Fang; James D. Ma; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Oil fields, hedge funds, and drugs. - Patrick Groeneveld; Rob A. Rutenbar; Jed W. Pitera; Erik C. Carlson; Jinsong Chen (DAC, 2009)

A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer. - Edward C. Lin; Rob A. Rutenbar (FPGA, 2009)

Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. - Xin Li 001; Rob A. Rutenbar; R. D. (Shawn) Blanton (ICCAD, 2009)

Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis. - Kai Yu; Rob A. Rutenbar (INTERSPEECH, 2009)

Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design. - Amith Singhee; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Novel Algorithms for Fast Statistical Analysis of Scaled Circuits - Amith Singhee; Rob A. Rutenbar (Springer, 2009)

Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference. - Wangyang Zhang; Xin Li 001; Rob A. Rutenbar (DAC, 2010)

Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation. - Wangyang Zhang; Xin Li 001; Emrah Acar; Frank Liu 001; Rob A. Rutenbar (ICCAD, 2010)

Analog layout synthesis: what's missing? - Rob A. Rutenbar (ISPD, 2010)

Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis. - Amith Singhee; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs. - Jiajing Wang; Amith Singhee; Rob A. Rutenbar; Benton H. Calhoun (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Toward efficient spatial variation decomposition via sparse regression. - Wangyang Zhang; Karthik Balakrishnan; Xin Li 001; Duane S. Boning; Rob A. Rutenbar (ICCAD, 2011)

Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. - Wangyang Zhang; Xin Li 001; Frank Liu 001; Emrah Acar; Rob A. Rutenbar; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers. - Jeffrey R. Johnston; Rob A. Rutenbar (ASAP, 2012)

Hardware implementation of MRF map inference on an FPGA platform. - Jungwook Choi; Rob A. Rutenbar (FPL, 2012)

Spatial variation decomposition via sparse regression. - Wangyang Zhang; Karthik Balakrishnan; Xin Li 001; Duane S. Boning; Emrah Acar; Frank Liu 001; Rob A. Rutenbar (ICICDT, 2012)

Stereophonic spectrogram segmentation using Markov random fields. - Minje Kim; Paris Smaragdis; Glenn G. Ko; Rob A. Rutenbar (MLSP, 2012)

Automatic clustering of wafer spatial signatures. - Wangyang Zhang; Xin Li 001; Sharad Saxena; Andrzej J. Strojwas; Rob A. Rutenbar (DAC, 2013)

EMERALD: Characterization of emerging applications and algorithms for low-power devices. - Chuanjun Zhang; Glenn G. Ko; Jungwook Choi; Shang-nien Tsai; Minje Kim; Abner Guzmán-Rivera; Rob A. Rutenbar; Paris Smaragdis; Mi Sun Park; Vijaykrishnan Narayanan; Hongyi Xin; Onur Mutlu; et al. (ISPASS, 2013)

FPGA acceleration of Markov Random Field TRW-S inference for stereo matching. - Jungwook Choi; Rob A. Rutenbar (MEMOCODE, 2013)

Error resilient MRF message passing architecture for stereo matching. - Jungwook Choi; Eric P. Kim; Rob A. Rutenbar; Naresh R. Shanbhag (SiPS, 2013)

Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression. - Wangyang Zhang; Karthik Balakrishnan; Xin Li 001; Duane S. Boning; Sharad Saxena; Andrzej J. Strojwas; Rob A. Rutenbar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Efficiently Enforcing Diversity in Multi-Output Structured Prediction. - Abner Guzmán-Rivera; Pushmeet Kohli; Dhruv Batra; Rob A. Rutenbar (AISTATS, 2014)

The First EDA MOOC: Teaching Design Automation to Planet Earth. - Rob A. Rutenbar (DAC, 2014)

A robust message passing based stereo matching kernel via system-level error resiliency. - Eric P. Kim; Jungwook Choi; Naresh R. Shanbhag; Rob A. Rutenbar (ICASSP, 2014)

DAC at 50: The Second 25 Years. - Rob A. Rutenbar (IEEE Des. Test, 2014)

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference. - Skand Hurkat; Jungwook Choi; Eriko Nurvitadhi; José F. Martínez; Rob A. Rutenbar (FPL, 2015)

Analog Circuit and Layout Synthesis Revisited. - Rob A. Rutenbar (ISPD, 2015)

Configurable and scalable belief propagation accelerator for computer vision. - Jungwook Choi; Rob A. Rutenbar (FPL, 2016)

Analysis of error resiliency of belief propagation in computer vision. - Jungwook Choi; Ameya D. Patil; Rob A. Rutenbar; Naresh R. Shanbhag (ICASSP, 2016)

Keynote address Wednesday: Hardware inference accelerators for machine learning. - Rob A. Rutenbar (ITC, 2016)

Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform. - Jungwook Choi; Rob A. Rutenbar (IEEE Trans. Circuits Syst. Video Technol., 2016)

Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching. - Eric P. Kim; Jungwook Choi; Naresh R. Shanbhag; Rob A. Rutenbar (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Toward a pixel-parallel architecture for graph cuts inference on FPGA. - Tianqi Gao; Jungwook Choi; Shang-nien Tsai; Rob A. Rutenbar (FPL, 2017)

A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference. - Glenn G. Ko; Rob A. Rutenbar (ICASSP, 2017)

Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA. - Sunwoong Kim; Rob A. Rutenbar (FCCM, 2018)

Realizing the potential of data science. - Francine Berman; Rob A. Rutenbar; Brent Hailpern; Henrik I. Christensen; Susan B. Davidson; Deborah Estrin; Michael J. Franklin; Margaret Martonosi; Padma Raghavan; Victoria Stodden; Alexander S. Szalay (Commun. ACM, 2018)

Real-Time and Low-Power Streaming Source Separation Using Markov Random Field. - Glenn G. Ko; Rob A. Rutenbar (ACM J. Emerg. Technol. Comput. Syst., 2018)

A Virtual Image Accelerator for Graph Cuts Inference on FPGA. - Tianqi Gao; Rob A. Rutenbar (ASAP, 2019)

FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs. - Glenn G. Ko; Yuji Chai; Rob A. Rutenbar; David Brooks 001; Gu-Yeon Wei (FCCM, 2019)

A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference. - Tianqi Gao; Rob A. Rutenbar (FPGA, 2019)

Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling. - Glenn G. Ko; Yuji Chai; Rob A. Rutenbar; David Brooks 001; Gu-Yeon Wei (FPL, 2019)

An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA. - Sunwoong Kim; Rob A. Rutenbar (ACM Great Lakes Symposium on VLSI, 2019)

FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption. - Sunwoong Kim; Keewoo Lee; Wonhee Cho 001; Jung Hee Cheon; Rob A. Rutenbar (ReConFig, 2019)

Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme. - Sunwoong Kim; Keewoo Lee; Wonhee Cho 001; Yujin Nam; Jung Hee Cheon; Rob A. Rutenbar (FCCM, 2020)

Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL. - Adel Ejjeh; Vikram S. Adve; Rob A. Rutenbar (FPGA, 2020)

A Scalable Bayesian Inference Accelerator for Unsupervised Learning. - Glenn G. Ko; Yuji Chai; Marco Donato; Paul N. Whatmough; Thierry Tambe; Rob A. Rutenbar; Gu-Yeon Wei; David Brooks 001 (Hot Chips Symposium, 2020)

A 3mm2 Programmable Bayesian Inference Accelerator for Unsupervised Machine Perception using Parallel Gibbs Sampling in 16nm. - Glenn G. Ko; Yuji Chai; Marco Donato; Paul N. Whatmough; Thierry Tambe; Rob A. Rutenbar; David Brooks 001; Gu-Yeon Wei (VLSI Circuits, 2020)

HPVM2FPGA: Enabling True Hardware-Agnostic FPGA Programming. - Adel Ejjeh; Leon Medvinsky; Aaron Councilman; Hemang Nehra; Suraj Sharma; Vikram S. Adve; Luigi Nardi; Eriko Nurvitadhi; Rob A. Rutenbar (ASAP, 2022)

Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers. - Sunwoong Kim; Cameron James Norris; James I. Oelund; Rob A. Rutenbar (IEEE Trans. Very Large Scale Integr. Syst., 2024)