Robert A. Walker

Affiliations:
  • Kent State University, OH, USA
  • Rensselaer Polytechnic Institute, Troy, NY, USA (1989 - 1996)
  • Carnegie-Mellon University, Pittsburgh, PA, USA (PhD 1988)


According to our database1, Robert A. Walker authored at least 31 papers between 1983 and 2011.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2011
MTASC: A Multithreaded Associative SIMD Processor.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

2008
Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor.
Parallel Process. Lett., 2008

Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
A Prototype Multithreaded Associative SIMD Processor.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache.
Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), 2006

2005
A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded Applications.
Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2005

2004
A Scalable Associative Processor with Applications in Database and Image Processing.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Cluster miss prediction for instruction caches in embedded networking applications.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

Cluster miss prediction with prefetch on miss for embedded CPU instruction caches.
Proceedings of the 2004 International Conference on Compilers, 2004

2003
Implementing a Scalable ASC Processor.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

2002
Implementing Associative Search and Responder Resolution.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001
Implementing Associative Processing: Rethinking EarlierArchitectural Decisions.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

2000
Efficient optimal design space characterization methodologies.
ACM Trans. Design Autom. Electr. Syst., 2000

1999
A practical one-semester "VLSI design" course for computer science (and other) majors.
Proceedings of the 30th SIGCSE Technical Symposium on Computer Science Education, 1999

Bounding Algorithms for Design Space Exploration.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Efficiently Searching the Optimal Design Space.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1997
A solution methodology for exact design space exploration in a three-dimensional design space.
IEEE Trans. Very Large Scale Integr. Syst., 1997

1996
Computing lower bounds on functional units before scheduling.
IEEE Trans. Very Large Scale Integr. Syst., 1996

Toward a Practical Methodology for Completely Characterizing the Optimal Design Space.
Proceedings of the 9th International Symposium on System Synthesis, 1996

1995
Introduction to the Scheduling Problem.
IEEE Des. Test Comput., 1995

An exact methodology for scheduling in a 3D design space.
Proceedings of the 8th International Symposium on System Synthesis (ISSS 1995), 1995

1994
Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem.
IEEE Trans. Very Large Scale Integr. Syst., 1994

ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis.
Proceedings of the Seventh International Conference on VLSI Design, 1994

1993
The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

Cluster-Oriented Scheduling in Pipelined Data Path Syntesis.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993

1991
Increasing User Interaction During High-Level Synthesis.
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, 1991

1989
Behavioral transformation for algorithmic level IC design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1988
The System Architect's Workbench.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1985
A model of design representation and synthesis.
Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1983
Automatic Data Path Synthesis.
Computer, 1983

Behavioral level transformation in the CMU-DA system.
Proceedings of the 20th Design Automation Conference, 1983


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