Behavioral level transformation in the CMU-DA system. - Robert A. Walker 001; Donald E. Thomas (DAC, 1983)

Automatic Data Path Synthesis. - Donald E. Thomas; Charles Y. Hitchcock III; Thaddeus J. Kowalski; Jayanth V. Rajan; Robert A. Walker 001 (Computer, 1983)

A model of design representation and synthesis. - Robert A. Walker 001; Donald E. Thomas (DAC, 1985)

The System Architect's Workbench. - Donald E. Thomas; Elizabeth M. Dirkes; Robert A. Walker 001; Jayanth V. Rajan; John A. Nestor; Robert L. Blackburn (DAC, 1988)

Behavioral transformation for algorithmic level IC design. - Robert A. Walker 001; Donald E. Thomas (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

Increasing User Interaction During High-Level Synthesis. - Robert A. Walker 001; Shivkumar Ramabadran; Rajive Joshi; Steinar Flatland (MICRO, 1991)

Cluster-Oriented Scheduling in Pipelined Data Path Syntesis. - Ching-Tang Chang; Kenneth Rose; Robert A. Walker 001 (ICCD, 1993)

The Structure of Assignment, Precedence, and Resource Constraints in the ILP Approach to the Scheduling Problem. - Samit Chaudhuri; Robert A. Walker 001; John Mitchell (ICCD, 1993)

ILP-Based Scheduling with Time and Resource Constraints in High Level Synthesis. - Samit Chaudhuri; Robert A. Walker 001 (VLSI Design, 1994)

Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem. - Samit Chaudhuri; Robert A. Walker 001; J. E. Mitchell (IEEE Trans. Very Large Scale Integr. Syst., 1994)

An exact methodology for scheduling in a 3D design space. - Samit Chaudhuri; Stephen A. Blythe; Robert A. Walker 001 (ISSS, 1995)

Introduction to the Scheduling Problem. - Robert A. Walker 001; Samit Chaudhuri (IEEE Des. Test Comput., 1995)

Toward a Practical Methodology for Completely Characterizing the Optimal Design Space. - Stephen A. Blythe; Robert A. Walker 001 (ISSS, 1996)

Computing lower bounds on functional units before scheduling. - Samit Chaudhuri; Robert A. Walker 001 (IEEE Trans. Very Large Scale Integr. Syst., 1996)

A solution methodology for exact design space exploration in a three-dimensional design space. - Samit Chaudhuri; S. A. Blthye; Robert A. Walker 001 (IEEE Trans. Very Large Scale Integr. Syst., 1997)

Efficiently Searching the Optimal Design Space. - Stephen A. Blythe; Robert A. Walker 001 (Great Lakes Symposium on VLSI, 1999)

Bounding Algorithms for Design Space Exploration. - Samit Chaudhuri; Robert A. Walker 001 (Great Lakes Symposium on VLSI, 1999)

A practical one-semester "VLSI design" course for computer science (and other) majors. - Robert A. Walker 001 (SIGCSE, 1999)

Efficient optimal design space characterization methodologies. - Stephen A. Blythe; Robert A. Walker 001 (ACM Trans. Design Autom. Electr. Syst., 2000)

Implementing Associative Processing: Rethinking EarlierArchitectural Decisions. - Robert A. Walker 001; Jerry L. Potter; Yanping Wang; Meiduo Wu (IPDPS, 2001)

Implementing Associative Search and Responder Resolution. - Meiduo Wu; Robert A. Walker 001; Jerry L. Potter (IPDPS, 2002)

Implementing a Scalable ASC Processor. - Hong Wang 007; Robert A. Walker 001 (IPDPS, 2003)

Cluster miss prediction with prefetch on miss for embedded CPU instruction caches. - Ken W. Batcher; Robert A. Walker 001 (CASES, 2004)

Cluster miss prediction for instruction caches in embedded networking applications. - Kenneth W. Batcher; Robert A. Walker 001 (ACM Great Lakes Symposium on VLSI, 2004)

A Scalable Associative Processor with Applications in Database and Image Processing. - Hong Wang 007; Lei Xie; Meiduo Wu; Robert A. Walker 001 (IPDPS, 2004)

A Scalable Pipelined Associative SIMD Array with Reconfigurable PE Interconnection Network for Embedded Applications. - Hong Wang 007; Robert A. Walker 001 (IASTED PDCS, 2005)

Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache. - Ken W. Batcher; Robert A. Walker 001 (IEEE Real Time Technology and Applications Symposium, 2006)

A Prototype Multithreaded Associative SIMD Processor. - Kevin Schaffer; Robert A. Walker 001 (IPDPS, 2007)

Dynamic Round-Robin Task Scheduling to Reduce Cache Misses for Embedded Systems. - Ken W. Batcher; Robert A. Walker 001 (DATE, 2008)

Using Hardware Multithreading to Overcome Broadcast/Reduction Latency in an Associative SIMD Processor. - Kevin Schaffer; Robert A. Walker 001 (Parallel Process. Lett., 2008)

MTASC: A Multithreaded Associative SIMD Processor. - Kevin Schaffer; Robert A. Walker 001 (IPDPS Workshops, 2011)