The Scalable Processor Architecture (SPARC). - Robert B. Garner; Anant Agrawal; Faye A. Briggs; Eric W. Brown 002; David Hough 001; Bill Joy 001; Steve R. Kleiman; Steven S. Muchnick; Masood Namjoo; David A. Patterson 001; Joan M. Pendleton; Richard Tuck (COMPCON, 1988)

SPARC: A scalable processor architecture. - Anant Agrawal; Robert B. Garner (Future Gener. Comput. Syst., 1992)

UltraSPARC: The Next Generation Superscalar 64-bit SPARC. - Dale Greenley; J. Bauman; D. Chang; Dennis Chen; R. Eltejaein; Philip A. Ferolito; P. Fu; Robert B. Garner; D. Greenhill; H. Grewal; Kalon Holdbrook; B. Kim; et al. (COMPCON, 1995)

Celebrating Chips and Architectures [Guest Editor's Introduction]. - Winfried W. Wilcke; Robert B. Garner (IEEE Micro, 1997)

Reliability of modular mesh-connected intelligent storage brick systems. - Claudio Fleiner; Robert B. Garner; James Lee Hafner; K. K. Rao; Deepak R. Kenchammana-Hosekote; Winfried W. Wilcke; Joseph S. Glider (IBM J. Res. Dev., 2006)

IBM Intelligent Bricks project - Petabytes and beyond. - Winfried W. Wilcke; Robert B. Garner; Claudio Fleiner; Richard F. Freitas; Richard A. Golding; Joseph S. Glider; Deepak R. Kenchammana-Hosekote; James Lee Hafner; K. Moidin Mohiuddin; K. K. Rao; Ralph A. Becker-Szendy; Theodore M. Wong; et al. (IBM J. Res. Dev., 2006)