A Comparison of Synchronous and Asynchronous FSMD Designs. - Richard Auletta; Robert B. Reese; Cherrice Traver (ICCD, 1993)

Developing and Distributing Component-Level VHDL Models. - J. Scott Calhoun; Vijay K. Madisetti; Robert B. Reese; Thomas Egolf (J. VLSI Signal Process., 1997)

User-configurable experimental design flows on the web: the ISCAS'99 experiments. - Hemang Lavana; Franc Brglez; Robert B. Reese (ISCAS (6), 1999)

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet. - Hemang Lavana; Franc Brglez; Robert B. Reese; Gangadhar Konduri; Anantha P. Chandrakasan (ICCD, 2000)

Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver (ICCD, 2001)

Generalized Early Evaluation in Self-Timed Circuits. - Mitchell A. Thornton; Kenneth Fazel; Robert B. Reese; Cherrice Traver (DATE, 2002)

PLFire: A Visualization Tool for Asynchronous Phased Logic Designs. - Kenneth Fazel; Mitchell A. Thornton; Robert B. Reese (DATE, 2003)

A Fine-Grain Phased Logic CPU. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver (ISVLSI, 2003)

Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. - Kenneth Fazel; Lun Li; Mitchell A. Thornton; Robert B. Reese; Cherrice Traver (ACM Great Lakes Symposium on VLSI, 2004)

Cooperative and progressive design experience for embedded systems. - Jerry W. Bruce; James C. Harden; Robert B. Reese (IEEE Trans. Educ., 2004)

A Coarse-Grain Phased Logic CPU. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver (IEEE Trans. Computers, 2005)

Early evaluation for performance enhancement in phased logic. - Robert B. Reese; Mitchell A. Thornton; Cherrice Traver; David Hemmendinger (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Introduction to Logic Synthesis using Verilog HDL - Robert B. Reese; Mitchell A. Thornton (Morgan & Claypool Publishers, 2006)

Finite State Machine Datapath Design, Optimization, and Implementation - Justin Davis; Robert B. Reese (Morgan & Claypool Publishers, 2007)

Uncle - An RTL Approach to Asynchronous Design. - Robert B. Reese; Scott C. Smith; Mitchell A. Thornton (ASYNC, 2012)

Setting the stage for CE2016: A revised body of knowledge. - Eric Durant; John Impagliazzo; Susan Conry; Robert B. Reese; Mitchell A. Thornton; Herman Lam; Victor P. Nelson (FIE, 2014)

CE2016: Updated computer engineering curriculum guidelines. - Eric Durant; John Impagliazzo; Susan Conry; Robert B. Reese; Herman Lam; Victor P. Nelson; Joseph L. Hughes; Weidong Liu; Junlin Lu; Andrew D. McGettrick (FIE, 2015)

CE2016 steering committee: a short update. - Susan Conry; Eric Durant; Herman Lam; Victor P. Nelson; Robert B. Reese (Inroads, 2015)