An Open-Source Scalable Thermal and Power Controller for HPC Processors. - Giovanni Bambini; Robert Balas; Christian Conficoni; Andrea Tilli; Luca Benini; Simone Benatti; Andrea Bartolini (ICCD, 2020)

RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis. - Robert Balas; Luca Benini (DATE, 2021)

Learning Affective Responses Through Evaluative Conditioning - New Developments in Affective Computing. - Robert Balas; Grzegorz Pochwatko (MIDI, 2021)

ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration. - Alessandro Ottaviano; Robert Balas; Giovanni Bambini; Corrado Bonfanti; Simone Benatti; Davide Rossi; Luca Benini; Andrea Bartolini (SAMOS, 2022)

Well-being in Isolation: Exploring Artistic Immersive Virtual Environments in a Simulated Lunar Habitat to Alleviate Asthenia Symptoms. - Grzegorz Pochwatko; Wieslaw Kopec; Justyna Swidrak; Anna Jaskulska; Kinga H. Skorupska; Barbara Karpowicz; Rafal Maslyk; Maciej Grzeszczuk; Steven Barnes; Paulina Borkiewicz; Pawel Kobylinski; Michal Pabis-Orzeszyna; et al. (ISMAR, 2023)

Towards a RISC-V Open Platform for Next-generation Automotive ECUs. - Luca Cuomo; Claudio Scordino; Alessandro Ottaviano; Nils Wistoff; Robert Balas; Luca Benini; Errico Guidieri; Ida Maria Savino (MECO, 2023)

AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs. - Thomas Benz; Alessandro Ottaviano; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Luca Benini (DATE, 2024)

PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors. - Alessandro Ottaviano; Robert Balas; Philippe Sauter; Manuel Eggimann; Luca Benini (DATE, 2024)

vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems. - Enrico Zelioli; Alessandro Ottaviano; Robert Balas; Nils Wistoff; Angelo Garofalo; Luca Benini (ICCD, 2024)

SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications. - Michael Rogenmoser; Alessandro Ottaviano; Thomas Benz; Robert Balas; Matteo Perotti; Angelo Garofalo; Luca Benini (CoRR, 2024)

ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package. - Alessandro Ottaviano; Robert Balas; Tim Fischer 001; Thomas Benz; Andrea Bartolini; Luca Benini (CoRR, 2024)

ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation. - Alessandro Ottaviano; Robert Balas; Giovanni Bambini; Antonio del Vecchio; Maicol Ciani; Davide Rossi; Luca Benini; Andrea Bartolini (Int. J. Parallel Program., 2024)

CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers. - Robert Balas; Alessandro Ottaviano; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2024)

CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor. - Christopher Reinwardt; Robert Balas; Alessandro Ottaviano; Angelo Garofalo; Luca Benini (CF, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems. - Thomas Benz; Alessandro Ottaviano; Chaoqun Liang; Robert Balas; Angelo Garofalo; Francesco Restuccia 002; Alessandro Biondi 001; Davide Rossi; Luca Benini (IEEE Trans. Computers, 2025)