State Assignment for PAL-based CPLDs. - Robert Czerwinski; Dariusz Kania (DSD, 2005)

CPLD-oriented Synthesis of Finite State Machines. - Robert Czerwinski; Dariusz Kania (DSD, 2009)

State machine description oriented towards effective usage of vendor-independent synthesis tools. - Robert Czerwinski; Józef Kulisz (PDeS, 2009)

State assignment and logic optimization for finite state machines. - Robert Czerwinski; Dariusz Kania (PDeS, 2009)

Synthesis of finite state machines for CPLDs. - Robert Czerwinski; Dariusz Kania (Int. J. Appl. Math. Comput. Sci., 2009)

The virtual drum kit. - Piotr Foltyn; Przemyslaw Flak; Robert Czerwinski; Tomasz Rudnicki (PDeS, 2010)

A PC-based object simulator for supporting PLC software development. - Józef Kulisz; Robert Czerwinski; Jan Mocha; Miroslaw Chmiel (PDeS, 2010)

Area and speed oriented synthesis of FSMs for PAL-based CPLDs. - Robert Czerwinski; Dariusz Kania (Microprocess. Microsystems, 2012)

FPGA Implementation of Programmable Logic Controller Compliant with EN 61131-3. - Robert Czerwinski; Miroslaw Chmiel; Wojciech Wygrabek (PDeS, 2013)

Performance analysis of a PMSM drive with torque and speed control. - Tomasz Rudnicki; Robert Czerwinski; Dariusz Polok; Andrzej Sikora (MIXDES, 2015)

An IEC 61131-3-based PLC implemented by means of an FPGA. - Miroslaw Chmiel; Józef Kulisz; Robert Czerwinski; A. Krzyzyk; Marcin Rosol; Patryk Smolarek (Microprocess. Microsystems, 2016)

State Assignment and Optimization of Ultra-High-Speed FSMs Utilizing Tristate Buffers. - Robert Czerwinski; Dariusz Kania (ACM Trans. Design Autom. Electr. Syst., 2016)