Comments on "Ternary Scan Design for VLSI Testability". - Robert F. Molyneaux; Alexander Albicki (IEEE Trans. Computers, 1989)

Efficient Testing of Clock Regenerator Circuits in Scan Designs. - Rajesh Raina; Robert Bailey; Charles Njinda; Robert F. Molyneaux; Charlie Beh (DAC, 1997)

How Seriously Do You Take Your Possible-Detect Faults? - Rajesh Raina; Charles Njinda; Robert F. Molyneaux (ITC, 1997)

Random Self-Test Method - Applications on PowerPC (tm) Microprocessor Caches. - Rajesh Raina; Robert F. Molyneaux (Great Lakes Symposium on VLSI, 1998)

DFT advances in the Motorola's MPC7400, a PowerPC G4 microprocessor. - Carol Pyron; Mike Alexander; James Golab; George Joos; Bruce Long; Robert F. Molyneaux; Rajesh Raina; Nandu Tendolkar (ITC, 1999)

DFT advances in Motorola's Next-Generation 74xx PowerPCTM microprocessor. - Rajesh Raina; Robert Bailey; Dawit Belete; Vikram Khosa; Robert F. Molyneaux; Javier Prado; Ashutosh Razdan (ITC, 2000)

At-Speed Testing of Delay Faults for Motorola's MPC7400, a PowerPC(tm) Microprocessor. - Nandu Tendolkar; Robert F. Molyneaux; Carol Pyron; Rajesh Raina (VTS, 2000)

Debug and Diagnosis in the Age of System-on-a-Chip. - Robert F. Molyneaux (ITC, 2003)

Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. - Robert F. Molyneaux; Thomas A. Ziaja; Hong Kim; Shahryar Aryani; Sungbae Hwang; Alex Hsieh (ITC, 2007)