Scaling to the End of Silicon with EDGE Architectures. - Doug Burger; Stephen W. Keckler; Kathryn S. McKinley; Michael Dahlin; Lizy Kurian John; Calvin Lin; Charles R. Moore; James H. Burrill; Robert G. McDonald; William Yode (Computer, 2004)

TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. - Karthikeyan Sankaralingam; Ramadass Nagarajan; Haiming Liu 001; Changkyu Kim; Jaehyuk Huh 001; Nitya Ranganathan; Doug Burger; Stephen W. Keckler; Robert G. McDonald; Charles R. Moore (ACM Trans. Archit. Code Optim., 2004)

Organization and implementation of the register-renaming mapper for out-of-order IBM POWER4 processors. - Taqi N. Buti; Robert G. McDonald; Zakaria Khwaja; Asit Ambekar; Hung Q. Le; William E. Burky; Bert Williams (IBM J. Res. Dev., 2005)

Implementation and Evaluation of On-Chip Network Architectures. - Paul Gratz; Changkyu Kim; Robert G. McDonald; Stephen W. Keckler; Doug Burger (ICCD, 2006)

Design and Implementation of the TRIPS Primary Memory System. - Simha Sethumadhavan; Robert G. McDonald; Rajagopalan Desikan; Doug Burger; Stephen W. Keckler (ICCD, 2006)

Critical path analysis of the TRIPS architecture. - Ramadass Nagarajan; Xia Chen; Robert G. McDonald; Doug Burger; Stephen W. Keckler (ISPASS, 2006)

Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. - Karthikeyan Sankaralingam; Ramadass Nagarajan; Robert G. McDonald; Rajagopalan Desikan; Saurabh Drolia; M. S. Govindan; Paul Gratz; Divya Gulati; Heather Hanson; Changkyu Kim; Haiming Liu 001; Nitya Ranganathan; et al. (MICRO, 2006)

Dataflow Predication. - Aaron Smith; Ramadass Nagarajan; Karthikeyan Sankaralingam; Robert G. McDonald; Doug Burger; Stephen W. Keckler; Kathryn S. McKinley (MICRO, 2006)

Implementation and Evaluation of a Dynamically Routed Processor Operand Network. - Paul Gratz; Karthikeyan Sankaralingam; Heather Hanson; Premkishore Shivakumar; Robert G. McDonald; Stephen W. Keckler; Doug Burger (NOCS, 2007)