Optical and Electrical Testing of Latchup in I/O Interface Circuits. - Franco Stellari; Peilin Song; Moyra K. McManus; Robert Gauthier 002; Alan J. Weger; Kiran V. Chatty; Mujahid Muhammad; Pia N. Sanda (ITC, 2003)

Latchup Analysis Using Emission Microscopy. - Franco Stellari; Peilin Song; Moyra K. McManus; Alan J. Weger; Robert Gauthier 002; Kiran V. Chatty; Mujahid Muhammad; Pia N. Sanda; Philip Wu; Steven C. Wilson (Microelectron. Reliab., 2003)

Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant. - David Alvarez; Michel J. Abou-Khalil; Christian Russ; Kiran V. Chatty; Robert Gauthier 002; D. Kontos; Junjun Li; Christopher Seguin; Ralph Halbach (Microelectron. Reliab., 2006)

Design automation to suppress cable discharge event (CDE) induced latchup in 90 nm CMOS ASICs. - Ciaran J. Brennan; Kiran V. Chatty; Jeff Sloan; Paul Dunn; Mujahid Muhammad; Robert Gauthier 002 (Microelectron. Reliab., 2007)

Implementation of diode and bipolar triggered SCRs for CDM robust ESD protection in 90 nm CMOS ASICs. - Ciaran J. Brennan; Shunhua Chang; Min Woo; Kiran V. Chatty; Robert Gauthier 002 (Microelectron. Reliab., 2007)

Design optimization of gate-silicided ESD NMOSFETs in a 45 nm bulk CMOS technology. - David Alvarez; Kiran V. Chatty; Christian Russ; Michel J. Abou-Khalil; Junjun Li; Robert Gauthier 002; Kai Esmark; Ralph Halbach; Christopher Seguin (Microelectron. Reliab., 2009)

Reliability aspects of gate oxide under ESD pulse stress. - Adrien Ille; Wolfgang Stadler; Thomas Pompl; Harald Gossner; Tilo Brodbeck; Kai Esmark; Philipp Riess; David Alvarez; Kiran V. Chatty; Robert Gauthier 002; Alain Bravaix (Microelectron. Reliab., 2009)

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond. - Ali Khaki-Firooz; Kangguo Cheng; Basanth Jagannathan; Pranita Kulkarni; Jeffrey W. Sleight; Davood Shahrjerdi; Josephine B. Chang; Sungjae Lee; Junjun Li; Huiming Bu; Robert Gauthier 002; Bruce Doris; et al. (ISSCC, 2010)

Simulation of ESD protection devices in an advanced CMOS technology using a TCAD workbench based on an ESD calibration methodology. - Tommaso Cilento; M. Schenkel; C. Yun; R. Mishra; Junjun Li; Kiran V. Chatty; Robert Gauthier 002 (Microelectron. Reliab., 2010)

Reducing the turn-on time and overshoot voltage for a diode-triggered silicon-controlled rectifier during an electrostatic discharge event. - Ahmed Ginawi; Tian Xia; Robert Gauthier 002 (SoCC, 2014)

Investigation of diode triggered silicon control rectifier turn-on time during ESD events. - Ahmed Y. Ginawi; Robert Gauthier 002; Tian Xia (SoCC, 2017)

A Novel HV-NPN ESD Protection Device with Buried Floating P-Type Implant. - Jie Jack Zeng; Ruchil Jain; Kyong Jin Hwang; Robert Gauthier 002 (IRPS, 2019)

ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies. - You Li; Meng Miao; Robert Gauthier 002 (CICC, 2020)

Design Optimization of MV-NMOS for ESD Self-protection in 28nm CMOS technology. - Kyong Jin Hwang; Sagar Premnath Karalkar; Vishal Ganesan; Sevashanmugam Marimuthu; Alban Zaka; Tom Herrmann; Bhoopendra Singh; Robert Gauthier 002 (IRPS, 2020)

Understanding ESD Induced Thermal Mechanism in FinFETs Through Predictive TCAD Simulation. - Zhiqing Li; Baofu Zhu; Anindya Nath; Meng Miao; Alain Loiseau; You Li; Jeffrey B. Johnson; Souvick Mitra; Robert Gauthier 002 (IRPS, 2020)

Design Optimization of MV-NMOS to Improve Holding Voltage of a 28nm CMOS Technology ESD Power Clamp. - Sagar Premnath Karalkar; Vishal Ganesan; Milova Paul; Kyong Jin Hwang; Robert Gauthier 002 (IRPS, 2021)