4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. - Robert Giterman; Adam Teman; Pascal Andreas Meinerzhagen; Andreas Burg 001; Alexander Fish (ISCAS, 2014)

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. - Adam Teman; Pascal Andreas Meinerzhagen; Robert Giterman; Alexander Fish; Andreas Burg 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. - Adam Teman; Georgios Karakonstantis; Robert Giterman; Pascal Andreas Meinerzhagen; Andreas Peter Burg (DATE, 2015)

Approximate computing with unreliable dynamic memories. - Shrikanth Ganapathy; Adam Teman; Robert Giterman; Andreas Burg 001; Georgios Karakonstantis (NEWCAS, 2015)

A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. - Robert Giterman; Adam Teman; Pascal Meinerzhagen; Alexander Fish; Andreas Burg 001 (ISCAS, 2016)

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. - Lior Atias; Adam Teman; Robert Giterman; Pascal Meinerzhagen; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. - Robert Giterman; Adam Teman; Pascal Andreas Meinerzhagen; Lior Atias; Andreas Burg 001; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. - Robert Giterman; Alexander Fish; Narkis Geuli; Elad Mentovich; Andreas Burg 001; Adam Teman (ESSCIRC, 2017)

Ultra miniature offset cancelled bandgap reference with ±0.534% inaccuracy from -10°C to 110°C. - Natan Vinshtok-Melnik; Robert Giterman; Joseph Shor (ISCAS, 2017)

Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. - Robert Giterman; Adam Teman; Pascal Meinerzhagen (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. - Robert Giterman; Lior Atias; Adam Teman (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. - Roman Golman; Robert Giterman; Adam Teman (ICECS, 2018)

High Density GC-eDRAM Design in 16nm FinFET. - Amir Shalom; Robert Giterman; Adam Teman (ICECS, 2018)

Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. - Robert Giterman; Roman Golman; Amir Shalom; Or Maltabashi; Alexander Fish; Adam Teman (ISCAS, 2018)

A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. - Or Maltabashi; Hanan Marinberg; Robert Giterman; Adam Teman (ISCAS, 2018)

An 800-MHz Mixed- VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications. - Robert Giterman; Alexander Fish; Narkis Geuli; Elad Mentovich; Andreas Burg 001; Adam Teman (IEEE J. Solid State Circuits, 2018)

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. - Robert Giterman; Alexander Fish; Andreas Burg 001; Adam Teman (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Gain-Cell Embedded DRAM-Based Physical Unclonable Function. - Robert Giterman; Yoav Weizman; Adam Teman (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Leakage Power Attack-Resilient Symmetrical 8T SRAM Cell. - Robert Giterman; Maoz Vicentowski; Itamar Levi; Yoav Weizman; Osnat Keren; Alexander Fish (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications. - Jonathan Narinx; Robert Giterman; Andrea Bonetti; Nicolas Frigerio; Cosimo Aprile; Andreas Burg 001; Yusuf Leblebici (A-SSCC, 2019)

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications. - Robert Giterman; Maoz Wicentowski; Oron Chertkow; Ilan Sever; Ishai Kehati; Yoav Weizman; Osnat Keren; Alexander Fish (ESSCIRC, 2019)

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection. - Robert Giterman; Roman Golman; Adam Teman (IEEE Access, 2019)

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. - Robert Giterman; Andrea Bonetti; Andreas Burg 001; Adam Teman (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 7T Security Oriented SRAM Bitcell. - Robert Giterman; Osnat Keren; Alexander Fish (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Lupulus: A Flexible Hardware Accelerator for Neural Networks. - Andreas Toftegaard Kristensen; Robert Giterman; Alexios Balatsoukas-Stimming; Andreas Burg 001 (ICASSP, 2020)

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. - Robert Giterman; Andrea Bonetti; Andreas Burg 001; Adam Teman (ISCAS, 2020)

Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique. - Roman Golman; Robert Giterman; Odem Harel; Adam Teman (ISCAS, 2020)

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM. - Odem Harel; Yarden Nachum; Robert Giterman (Microelectron. J., 2020)

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. - Robert Giterman; Andrea Bonetti; Ester Vicario Bravo; Tzachi Noy; Adam Teman; Andreas Burg 001 (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Gain-Cell Embedded DRAMs: Modeling and Design Space. - Andrea Bonetti; Roman Golman; Robert Giterman; Adam Teman; Andreas Burg 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros. - Roman Golman; Netanel Nachum; Tomer Cohen; Robert Giterman; Adam Teman (IEEE Access, 2021)

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads. - Yoav Weizman; Robert Giterman; Oron Chertkow; Maoz Wicentowski; Itamar Levi; Ilan Sever; Ishai Kehati; Osnat Keren; Alexander Fish (IEEE Access, 2021)

A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time. - Odem Harel; Halil Andaç Yigit; Eliana Feifel; Robert Giterman; Andreas Burg 001; Adam Teman (IEEE J. Solid State Circuits, 2025)