Gate matrix layout of random control logic in a 32-bit CMOS CPU chip adaptable to evolving logic design. - Sung-Mo Kang; Robert H. Krambeck; Hung-Fai Stephen Law (DAC, 1982)

Gate Matrix Layout of Random Control Logic in a 32-bit CMOS CPU Chip Adaptable to Evolving Logic Design. - Sung-Mo Kang; Robert H. Krambeck; Hung-Fai Stephen Law; Alexander D. Lopez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

A content addressable memory management unit with on-chip data cache. - A. Kemal Goksel; Robert H. Krambeck; Philipp P. Thomas; Mean-Sea Tsay; Cheng Yueh Chen; Donald G. Clemons; Frank D. LaRocca; Liang-Peng Mai (IEEE J. Solid State Circuits, 1989)