A polynomial-based division algorithm. - Robert Hägglund; Per Löwenborg; Mark Vesterbacka (ISCAS (3), 2002)

Design Space Exploration and Trade-Offs in Analog Amplifier Design. - Emil Hjalmarson; Robert Hägglund; Lars Wanhammar (PATMOS, 2003)

Design of a reference voltage buffer for a 10-bit 1-MS/s SAR ADC. - Prakash Harikumar; Pavel Angelov; Robert Hägglund (MIXDES, 2014)

A Bang-Bang Digital PLL Covering 11.1-14.3 GHz and 14.7-18.7 GHz with sub-40 fs RMS Jitter in 7 nm FinFET Technology. - Staffan Ek; Patrik Karlsson; Andreas Kämpe; Roland Strandberg; Aravind Tharayil Narayanan; Martin Anderson; Hind Dafallah; Mesrop Daghbashyan; Tayebeh Ghanavati Nejad; Robert Hägglund; Nikola Ivanisevic; Robert Nilsson; et al. (ESSCIRC, 2022)

A 12/16 GSps Time-Interleaved Pipelined-SAR ADC with Temperature Robust Performance at 0.75V Supply in 7nm FinFET Technology. - Mattias Palm; Daniele Mastantuono; Christer Jansson; Erik Backenius; Nikola Ivanisevic; Mikael Normark; Prakash Harikumar; My-Chien Yee; Andreas Leidenhed; Roland Strandberg; Sunny Sharma; Hanie Ghaedrahmati; et al. (ESSCIRC, 2023)