1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro. - Osamu Takahashi; Sang H. Dhong; Manabu Ohkubo; Shohji Onishi; Robert H. Dennard; Robert Hannon; Scott Crowder; Subramanian S. Iyer; Matthew R. Wordeman; Bijan Davari; William B. Weinberger; Naoaki Aoki (IEEE J. Solid State Circuits, 2000)

Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment. - Gweltaz Gaudin; Gregory Riou; Didier Landru; Catherine Tempesta; Ionut Radu; Mariam Sadaka; Kevin Winstel; Emily Kinser; Robert Hannon (3DIC, 2010)

Pre bonding metrology solutions for 3D integration. - Gregory Riou; Gweltaz Gaudin; Didier Landru; Catherine Tempesta; Ionut Radu; Mariam Sadaka; Kevin Winstel; Emily Kinser; Robert Hannon; Boris V. Kamenev; Michael Darwin; Robert Sachs (3DIC, 2010)

Spatial and temporal thermal characterization of stacked multicore architectures. - Eren Kursun; Jamil A. Wakil; Mukta Farooq; Robert Hannon (ACM J. Emerg. Technol. Comput. Syst., 2012)