SAT-Based ATPG for Zero-Aliasing Compaction. - Robert Hülle; Petr Fiser; Jan Schmidt (DSD, 2017)

ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction. - Robert Hülle; Petr Fiser; Jan Schmidt (Microprocess. Microsystems, 2018)

Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. - Jaroslav Borecký; Robert Hülle; Petr Fiser (DSD, 2020)

Reducing Output Response Aliasing Using Boolean Optimization Techniques. - Robert Hülle; Petr Fiser; Jan Schmidt (DDECS, 2023)

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA. - Miroslav Skrbek; Pavel Kubalík; Martin Kohlík; Jaroslav Borecký; Robert Hülle (MECO, 2023)

Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA. - Miroslav Skrbek; Pavel Kubalík; Martin Kohlík; Jaroslav Borecký; Robert Hülle (MECO, 2024)