Functional testing of TFT/LCD arrays. - Leslie C. Jenkins; Robert J. Polastre; Ronald R. Troutman; Robert L. Wisnieff (IBM J. Res. Dev., 1992)

A 10.5-in.-diagonal SXGA active-matrix display. - Evan G. Colgan; Paul M. Alt; Robert L. Wisnieff; Peter M. Fryer; Eileen A. Galligan; William S. Graham; Paul F. Greier; Raymond R. Horton; Harold Ifill; Leslie C. Jenkins; Richard A. John; Richard I. Kaufman; et al. (IBM J. Res. Dev., 1998)

Thin-film-transistor process-characterization test structures. - Evan G. Colgan; Robert J. Polastre; Masatomo Takeichi; Robert L. Wisnieff (IBM J. Res. Dev., 1998)

Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology. - John U. Knickerbocker; Chirag S. Patel; Paul S. Andry; Cornelia K. Tsang; L. Paivikki Buchwalter; Edmund J. Sprogis; Hua Gan; Raymond R. Horton; Robert J. Polastre; Steven L. Wright; Christian D. Schuster; Christian W. Baks; et al. (CICC, 2005)

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection. - John U. Knickerbocker; Paul S. Andry; L. Paivikki Buchwalter; Alina Deutsch; Raymond R. Horton; Keith A. Jenkins; Young Hoon Kwark; Gerald McVicker; Chirag S. Patel; Robert J. Polastre; Christian D. Schuster; Arun Sharma; et al. (IBM J. Res. Dev., 2005)

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias. - John U. Knickerbocker; Chirag S. Patel; Paul S. Andry; Cornelia K. Tsang; L. Paivikki Buchwalter; Edmund J. Sprogis; Hua Gan; Raymond R. Horton; Robert J. Polastre; Steven L. Wright; John M. Cotte (IEEE J. Solid State Circuits, 2006)

3D chip stacking with C4 technology. - Bing Dang; Steven L. Wright; Paul S. Andry; Edmund J. Sprogis; Cornelia K. Tsang; M. John Interrante; Bucknell C. Webb; Robert J. Polastre; Raymond R. Horton; Chirag S. Patel; Arun Sharma; J. Zheng; et al. (IBM J. Res. Dev., 2008)

Three-dimensional silicon integration. - John U. Knickerbocker; Paul S. Andry; Bing Dang; Raymond R. Horton; Mario J. Interrante; Chirag S. Patel; Robert J. Polastre; Katsuyuki Sakuma; Ranjani Sirdeshmukh; Edmund J. Sprogis; Sri M. Sri-Jayantha; Antonio M. Stephens; et al. (IBM J. Res. Dev., 2008)

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. - Katsuyuki Sakuma; Paul S. Andry; Cornelia K. Tsang; Steven L. Wright; Bing Dang; Chirag S. Patel; Bucknell C. Webb; J. Maria; Edmund J. Sprogis; S. K. Kang; Robert J. Polastre; Raymond R. Horton; et al. (IBM J. Res. Dev., 2008)