An Analysis of the Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel-Diode Circuit. - Robert K. Brayton; Ralph A. Willoughby (IEEE Trans. Electron. Comput., 1963)

Stability Criteria for Large Networks. - Robert K. Brayton (IBM J. Res. Dev., 1964)

Logic Minimization Algorithms for VLSI Synthesis - Robert K. Brayton; Gary D. Hachtel; Curtis T. McMullen; Alberto L. Sangiovanni-Vincentelli (Springer, 1984)

Optimal State Assignment for Finite State Machines. - Giovanni De Micheli; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985)

Correction to "Optimal State Assignment for Finite State Machines". - Giovanni De Micheli; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986)

MIS: A Multiple-Level Logic Optimization System. - Robert K. Brayton; Richard L. Rudell; Alberto L. Sangiovanni-Vincentelli; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987)

XPSim: a MOS VLSI simulator. - Romy L. Bauer; Jiayuan Fang; Antony P.-C. Ng; Robert K. Brayton (ICCAD, 1988)

Don't cares and global flow analysis of Boolean networks. - Robert K. Brayton; Ellen M. Sentovich; Fabio Somenzi (ICCAD, 1988)

A modified approach to two-level logic minimization. - Abdul A. Malik; Robert K. Brayton; A. Richard Newton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

Logic verification using binary decision diagrams in a logic synthesis environment. - Sharad Malik; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

Timing optimization of combinational logic. - Kanwar Jit Singh; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1988)

Multi-level logic minimization using implicit don't cares. - Karen A. Bartlett; Robert K. Brayton; Gary D. Hachtel; Reily M. Jacoby; Christopher R. Morrison; Richard L. Rudell; Alberto L. Sangiovanni-Vincentelli; Albert R. Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Efficient Prime Factorization of Logic Expressions. - Patrick C. McGeer; Robert K. Brayton (DAC, 1989)

Efficient Algorithms for Computing the Longest Viable Path in a Combinational Network. - Patrick C. McGeer; Robert K. Brayton (DAC, 1989)

Multi-level Logic Simplification Using Don't Cares and Filters. - Alexander Saldanha; Albert R. Wang; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1989)

SLIP: a software environment for system level interactive partitioning. - Mark Beardslee; Chuck Kring; Rajeev Murgai; Hamid Savoj; Robert K. Brayton; A. Richard Newton (ICCAD, 1989)

An exact minimizer for Boolean relations. - Robert K. Brayton; Fabio Somenzi (ICCAD, 1989)

Consistency and observability invariance in multi-level logic synthesis. - Patrick C. McGeer; Robert K. Brayton (ICCAD, 1989)

Fast two-level logic minimizers for multi-level logic synthesis. - Hamid Savoj; Abdul A. Malik; Robert K. Brayton (ICCAD, 1989)

Logic minimization for factored forms. - Abdul A. Malik; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1989)

Reduced Offsets for Two-Level Multi-Valued Logic Minimization. - Abdul A. Malik; Robert K. Brayton; A. Richard Newton; Alberto L. Sangiovanni-Vincentelli (DAC, 1990)

Timing Analysis in Precharge/Unate Networks. - Patrick C. McGeer; Robert K. Brayton (DAC, 1990)

Logic Synthesis for Programmable Gate Arrays. - Rajeev Murgai; Yoshihito Nishizaki; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1990)

The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. - Hamid Savoj; Robert K. Brayton (DAC, 1990)

MIS-MV: Optimization of Multi-Level Logic with Multiple-Valued Inputs. - Luciano Lavagno; Sharad Malik; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

Performance Optimization of Pipelined Circuits. - Sharad Malik; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

Timing Optimization with Testability Considerations. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli; Kwang-Ting Cheng (ICCAD, 1990)

Algorithms for Discrete Function Manipulation. - Arvind Srinivasan 004; Timothy Kam; Sharad Malik; Robert K. Brayton (ICCAD, 1990)

Implicit State Enumeration of Finite State Machines Using BDDs. - Hervé J. Touati; Hamid Savoj; Bill Lin 001; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

The observability don't-care set and its approximations. - Patrick C. McGeer; Robert K. Brayton (ICCD, 1990)

Multilevel logic synthesis. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli (Proc. IEEE, 1990)

A Framework for Satisfying Input and Output Encoding Constraints. - Alexander Saldanha; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1991)

Performance Enhancement through the Generalized Bypass Transform. - Patrick C. McGeer; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli; Sartaj Sahni (ICCAD, 1991)

Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. - Patrick C. McGeer; Alexander Saldanha; Paul R. Stephan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. - Cho W. Moon; Paul R. Stephan; Robert K. Brayton (ICCAD, 1991)

On Clustering for Minimum Delay/Area. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Improved Logic Synthesis Algorithms for Table Look Up Architectures. - Rajeev Murgai; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. - Rajeev Murgai; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Observability Relations and Observability Don't Cares. - Hamid Savoj; Robert K. Brayton (ICCAD, 1991)

Extracting Local Don't Cares for Network Optimization. - Hamid Savoj; Robert K. Brayton; Hervé J. Touati (ICCAD, 1991)

Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. - Hervé J. Touati; Hamid Savoj; Robert K. Brayton (ICCAD, 1991)

Heuristic Minimazation of Multiple-Valued Relations. - Yosinori Watanabe; Robert K. Brayton (ICCAD, 1991)

Three-Level Decomposition with Application to PLDs. - Abdul A. Malik; David Harrison; Robert K. Brayton (ICCD, 1991)

Retiming of Circuits with Single Phase Transparent Latches. - Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1991)

Incremental Synthesis for Engineering Changes. - Yosinori Watanabe; Robert K. Brayton (ICCD, 1991)

Preserving Don't Care Conditions During Retiming. - Ellen Sentovich; Robert K. Brayton (VLSI, 1991)

Reduced offsets for minimization of binary-valued functions. - Abdul A. Malik; Robert K. Brayton; A. Richard Newton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Retiming and resynthesis: optimizing sequential networks with combinational techniques. - Sharad Malik; Ellen M. Sentovich; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Efficient omega-Regular Language Containment. - Ramin Hojati; Hervé J. Touati; Robert P. Kurshan; Robert K. Brayton (CAV, 1992)

Automatic Reduction in CTL Compositional Model Checking. - Thomas R. Shiple; Massimiliano Chiodo; Alberto L. Sangiovanni-Vincentelli; Robert K. Brayton (CAV, 1992)

Solving the State Assignment Problem for Signal Transition Graphs. - Luciano Lavagno; Cho W. Moon; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

An Improved Synthesis Algorithm for Multiplexor-Based PGA's. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

On the Temporal Equivalence of Sequential Circuits. - Narendra V. Shenoy; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1992)

Boolean matching in logic synthesis. - Hamid Savoj; Mário J. Silva; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (EURO-DAC, 1992)

Automatic compositional minimization in CTL model checking. - Massimiliano Chiodo; Thomas R. Shiple; Alberto L. Sangiovanni-Vincentelli; Robert K. Brayton (ICCAD, 1992)

Valid clocking in wavepipelined circuits. - William K. C. Lam; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1992)

Graph algorithms for clock schedule optimization. - Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1992)

Delay Prediction for Technology-Independent Logic Equations. - Paul T. Gutwin; Patrick C. McGeer; Robert K. Brayton (ICCD, 1992)

On Relationship Between ITE and BDD. - William K. C. Lam; Robert K. Brayton (ICCD, 1992)

Sequential Circuit Design Using Synthesis and Optimization. - Ellen Sentovich; Kanwar Jit Singh; Cho W. Moon; Hamid Savoj; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1992)

Symbolic minimization of multilevel logic and the input encoding problem. - Sharad Malik; Luciano Lavagno; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Logic Synthesis and Design Verification. - Robert K. Brayton (CAV, 1993)

BDD-Based Debugging Of Design Using Language Containment and Fair CTL. - Ramin Hojati; Robert K. Brayton; Robert P. Kurshan (CAV, 1993)

Alternating RQ Timed Automata. - William K. C. Lam; Robert K. Brayton (CAV, 1993)

A Unified Approach to Language Containment and Fair CTL Model Checking. - Ramin Hojati; Thomas R. Shiple; Robert K. Brayton; Robert P. Kurshan (DAC, 1993)

Circuit Delay Models and Their Exact Computation Using Timed Boolean Functions. - William K. C. Lam; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1993)

Delay Fault Coverage and Performance Tradeoffs. - William K. C. Lam; Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1993)

On Computing the Transitive Closure of a State Transition Relation. - Yusuke Matsunaga; Patrick C. McGeer; Robert K. Brayton (DAC, 1993)

Elimination of Dynamic hazards by Factoring. - Cho W. Moon; Robert K. Brayton (DAC, 1993)

Sequential Synthesis for Table Look Up Programmable Gate Arrays. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1993)

Resynthesis of Multi-Phase Pipelines. - Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1993)

Dynamic variable reordering for BDD minimization. - Eric Felt; Gary York; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (EURO-DAC, 1993)

Cube-packing and two-level minimization. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1993)

Minimum padding to satisfy short path constraints. - Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1993)

Input don't care sequences in FSM networks. - Huey-Yih Wang; Robert K. Brayton (ICCAD, 1993)

The maximum set of permissible behaviors for FSM networks. - Yosinori Watanabe; Robert K. Brayton (ICCAD, 1993)

Some Results on the Complexity of Boolean Functions for Table Look Up Architectures. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1993)

Heuristic Minimization of Synchronous Relations. - Vigyan Singhal; Yosinori Watanabe; Robert K. Brayton (ICCD, 1993)

Physically Realizable Gate Models. - Paul R. Stephan; Robert K. Brayton (ICCD, 1993)

Logic Optimization with Multi-Output Gates. - Yosinori Watanabe; Lisa M. Guerra; Robert K. Brayton (ICCD, 1993)

Minimization of Logic Functions Using Essential Signature Sets. - Patrick C. McGeer; Jagesh V. Sanghavi; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1993)

Two-Level Minimization of Multivalued Functions with Large Offsets. - Abdul A. Malik; Robert K. Brayton; A. Richard Newton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Computers, 1993)

Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis. - Sharad Malik; Kanwar Jit Singh; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Computing the initial states of retimed circuits. - Hervé J. Touati; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Heuristic minimization of multiple-valued relations. - Yosinori Watanabe; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

ESPRESSO-SIGNATURE: a new exact minimizer for logic functions. - Patrick C. McGeer; Jagesh V. Sanghavi; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Timed Boolean functions - a unified formalism for exact timing analysis. - William K. C. Lam; Robert K. Brayton (Kluwer, 1994)

Improving Language Containment Using Fairness Graphs. - Ramin Hojati; Robert B. Mueller-Thuns; Robert K. Brayton (CAV, 1994)

Criteria for the Simple Path Property in Timed Automata. - William K. C. Lam; Robert K. Brayton (CAV, 1994)

HSIS: A BDD-Based Environment for Formal Verification. - Adnan Aziz; Felice Balarin; Szu-Tsung Cheng; Ramin Hojati; Timothy Kam; Sriram C. Krishnan; Rajeev K. Ranjan 001; Thomas R. Shiple; Vigyan Singhal; Serdar Tasiran; Huey-Yih Wang; Robert K. Brayton; et al. (DAC, 1994)

BDD Variable Ordering for Interacting Finite State Machines. - Adnan Aziz; Serdar Tasiran; Robert K. Brayton (DAC, 1994)

A Fully Implicit Algorithm for Exact State Minimization. - Timothy Kam; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1994)

Exact Minimum Cycle Times for Finite State Machines. - William K. C. Lam; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1994)

Optimum Functional Decomposition Using Encoding. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1994)

Performance Optimization Using Exact Sensitization. - Alexander Saldanha; Heather Harkness; Patrick C. McGeer; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1994)

Heuristic Minimization of BDDs Using Don't Cares. - Thomas R. Shiple; Ramin Hojati; Alberto L. Sangiovanni-Vincentelli; Robert K. Brayton (DAC, 1994)

Permissible Observability Relations in FSM Networks. - Huey-Yih Wang; Robert K. Brayton (DAC, 1994)

State Minimization of Pseudo Non-Deterministic FSM's. - Yosinori Watanabe; Robert K. Brayton (EDAC-ETC-EUROASIC, 1994)

A redesign technique for combinational circuits based on gate reconnections. - Yuji Kukimoto; Masahiro Fujita; Robert K. Brayton (ICCAD, 1994)

Multi-level synthesis for safe replaceability. - Carl Pixley; Vigyan Singhal; Adnan Aziz; Robert K. Brayton (ICCAD, 1994)

Incremental formal design verification. - Gitanjali Swamy; Robert K. Brayton (ICCAD, 1994)

Minimizing Interacting Finite State Machines: A Compositional Approach to Language to Containment. - Adnan Aziz; Vigyan Singhal; Gitanjali Swamy; Robert K. Brayton (ICCD, 1994)

An Exact Optimization of Two-Level Acyclic Sequential Circuits. - Ellen Sentovich; Robert K. Brayton (ICCD, 1994)

Deterministic w Automata vis-a-vis Deterministic Buchi Automata. - Sriram C. Krishnan; Anuj Puri; Robert K. Brayton (ISAAC, 1994)

Circuit structure relations to redundancy and delay. - Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Satisfaction of input and output encoding constraints. - Alexander Saldanha; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Specification, synthesis, and verification of hazard-free asynchronous circuits. - Cho W. Moon; Paul R. Stephan; Robert K. Brayton (J. VLSI Signal Process., 1994)

Supervisory Control of Finite State Machines. - Adnan Aziz; Felice Balarin; Robert K. Brayton; Marika Domenica Di Benedetto; Alexander Saldanha (CAV, 1995)

Automatic Datapath Abstraction In Hardware Systems. - Ramin Hojati; Robert K. Brayton (CAV, 1995)

The Rabin Index and Chain Automata, with Applications to Automatas and Games. - Sriram C. Krishnan; Anuj Puri; Robert K. Brayton; Pravin Varaiya (CAV, 1995)

Language containment of non-deterministic omega-automata. - Serdar Tasiran; Ramin Hojati; Robert K. Brayton (CHARME, 1995)

The Validity of Retiming Sequential Circuits. - Vigyan Singhal; Carl Pixley; Richard L. Rudell; Robert K. Brayton (DAC, 1995)

Decomposition of logic functions for minimum transition activity. - Rajeev Murgai; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ED&TC, 1995)

Exploiting power-up delay for sequential optimization. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Robert K. Brayton (EURO-DAC, 1995)

Multi-level logic optimization of FSM networks. - Huey-Yih Wang; Robert K. Brayton (ICCAD, 1995)

Implicit state minimization of non-deterministic FSMs. - Timothy Kam; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1995)

Incremental methods for FSM traversal. - Gitanjali Swamy; Robert K. Brayton; Vigyan Singhal (ICCD, 1995)

Power-Up Delay for Retiming Digital Circuits. - Vigyan Singhal; Robert K. Brayton; Carl Pixley (ISCAS, 1995)

Structural Complexity of Omega-Automata. - Sriram C. Krishnan; Anuj Puri; Robert K. Brayton (STACS, 1995)

Functional clock schedule optimization. - Alexander Saldanha; Narendra V. Shenoy; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1995)

An Environment for Formal Verification Based on Symbolic Computations. - Ramin Hojati; Robert K. Brayton (Formal Methods Syst. Des., 1995)

Network Hierarchies and Node Minimization. - Robert K. Brayton; Ellen M. Sentovich (IEICE Trans. Inf. Syst., 1995)

Delay fault coverage, test set size, and performance trade-offs. - William K. C. Lam; Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

An efficient heuristic procedure for solving the state assignment problem for event-based specifications. - Luciano Lavagno; Cho W. Moon; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Testing Language Containment for omega-Automata Using BDD's - Hervé J. Touati; Robert K. Brayton; Robert P. Kurshan (Inf. Comput., 1995)

Verifying Continuous Time Markov Chains. - Adnan Aziz; Kumud Sanwal; Vigyan Singhal; Robert K. Brayton (CAV, 1996)

VIS: A System for Verification and Synthesis. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (CAV, 1996)

Verifying Abstractions of Timed Systems. - Serdar Tasiran; Rajeev Alur; Robert P. Kurshan; Robert K. Brayton (CONCUR, 1996)

Engineering Change in a Non-Deterministic FSM Setting. - Sunil P. Khatri; Amit Narayan; Sriram C. Krishnan; Kenneth L. McMillan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1996)

High Performance BDD Package By Exploiting Memory Hiercharchy. - Jagesh V. Sanghavi; Rajeev K. Ranjan 001; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (DAC, 1996)

Incremental re-encoding for symbolic traversal of product machines. - Gianpiero Cabodi; Paolo Camurati; Luciano Lavagno; Stefano Quer; Robert K. Brayton; Ellen Sentovich (EURO-DAC, 1996)

VIS. - Robert K. Brayton; Gary D. Hachtel; Alberto L. Sangiovanni-Vincentelli; Fabio Somenzi; Adnan Aziz; Szu-Tsung Cheng; Stephen A. Edwards; Sunil P. Khatri; Yuji Kukimoto; Abelardo Pardo; Shaz Qadeer; Rajeev K. Ranjan 001; et al. (FMCAD, 1996)

Verification Using Uninterpreted Functions and Finite Instantiations. - Ramin Hojati; Adrian J. Isles; Desmond Kirkpatrick; Robert K. Brayton (FMCAD, 1996)

Decomposition Techniques for Efficient ROBDD Construction. - Jawahar Jain; Amit Narayan; C. Coelho 001; Sunil P. Khatri; Alberto L. Sangiovanni-Vincentelli; Robert K. Brayton; Masahiro Fujita (FMCAD, 1996)

The case for retiming with explicit reset circuitry. - Vigyan Singhal; Sharad Malik; Robert K. Brayton (ICCAD, 1996)

Early Quantification and Partitioned Transition Relations. - Ramin Hojati; Sriram C. Krishnan; Robert K. Brayton (ICCD, 1996)

Latch Redundancy Removal Without Global Reset. - Shaz Qadeer; Robert K. Brayton; Vigyan Singhal (ICCD, 1996)

Binary decision diagrams on network of workstation. - Rajeev K. Ranjan 001; Jagesh V. Sanghavi; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1996)

A study of composition schemes for mixed apply/compose based construction of ROBDDs. - Amit Narayan; Sunil P. Khatri; Jawahar Jain; Masahiro Fujita; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1996)

Valid clock frequencies and their computation in wavepipelined circuits. - William K. C. Lam; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Combinational test generation using satisfiability. - Paul R. Stephan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Permissible functions for multioutput components in combinational logic optimization. - Yosinori Watanabe; Lisa M. Guerra; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

STARI: A Case Study in Compositional and Hierarchical Timing Verification. - Serdar Tasiran; Robert K. Brayton (CAV, 1997)

Exact Required Time Analysis via False Path Detection. - Yuji Kukimoto; Robert K. Brayton (DAC, 1997)

Negative thinking by incremental problem solving: application to unate covering. - Evguenii I. Goldberg; Luca P. Carloni; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

A fast and robust exact algorithm for face embedding. - Evguenii I. Goldberg; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

Approximate timing analysis of combinational circuits under the XBD0 model. - Yuji Kukimoto; Wilsin Gosti; Alexander Saldanha; Robert K. Brayton (ICCAD, 1997)

Sequential optimisation without state space exploration. - Amit Mehrotra; Shaz Qadeer; Vigyan Singhal; Robert K. Brayton; Adnan Aziz; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

Reachability analysis using partitioned-ROBDDs. - Amit Narayan; Adrian J. Isles; Jawahar Jain; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1997)

Timed Binary Decision Diagrams. - Zhongcheng Li; Yuhong Zhao; Yinghua Min; Robert K. Brayton (ICCD, 1997)

Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. - Rajeev K. Ranjan 001; Wilsin Gosti; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1997)

Efficient Identification of Non-Robustly Untestable Path Delay Faults. - Zhongcheng Li; Robert K. Brayton; Yinghua Min (ITC, 1997)

Implicit computation of compatible sets for state minimization of ISFSMs. - Timothy Kam; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Theory and algorithms for state minimization of nondeterministic FSMs. - Timothy Kam; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Explicit and implicit algorithms for binate covering problems. - Tiziano Villa; Timothy Kam; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Symbolic two-level minimization. - Tiziano Villa; Alexander Saldanha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

A New Low-Cost Method for Identifying Untestable Path Delay Faults. - Zhongcheng Li; Yinghua Min; Robert K. Brayton (Asian Test Symposium, 1998)

Computing Reachable Control States of Systems Modeled with Uninterpreted Functions and Infinite Memory. - Adrian J. Isles; Ramin Hojati; Robert K. Brayton (CAV, 1998)

Structural Symmetry and Model Checking. - Gurmeet Singh Manku; Ramin Hojati; Robert K. Brayton (CAV, 1998)

Hierarchical Functional Timing Analysis. - Yuji Kukimoto; Robert K. Brayton (DAC, 1998)

Delay-Optimal Technology Mapping by DAG Covering. - Yuji Kukimoto; Robert K. Brayton; Prashant Sawkar (DAC, 1998)

Planning for Performance. - Ralph H. J. M. Otten; Robert K. Brayton (DAC, 1998)

Combinational Verification based on High-Level Functional Specifications. - Evguenii I. Goldberg; Yuji Kukimoto; Robert K. Brayton (DATE, 1998)

Wireplanning in logic synthesis. - Wilsin Gosti; Amit Narayan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1998)

On the optimization power of retiming and resynthesis transformations. - Rajeev K. Ranjan 001; Vigyan Singhal; Fabio Somenzi; Robert K. Brayton (ICCAD, 1998)

Implementation and use of SPFDs in optimizing Boolean networks. - Subarnarekha Sinha; Robert K. Brayton (ICCAD, 1998)

Efficient Verification and Synthesis using Design Commonalities. - Gitanjali Swamy; Stephen A. Edwards; Robert K. Brayton (VLSI Design, 1998)

Theory and algorithms for face hypercube embedding. - Evguenii I. Goldberg; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

A Novel VLSI Layout Fabric for Deep Sub-Micron Applications. - Sunil P. Khatri; Amit Mehrotra; Robert K. Brayton; Ralph H. J. M. Otten; Alberto L. Sangiovanni-Vincentelli (DAC, 1999)

Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints. - Abdallah Tabbara; Robert K. Brayton; A. Richard Newton (DAC, 1999)

Using Combinational Verification for Sequential Circuits. - Rajeev K. Ranjan 001; Vigyan Singhal; Fabio Somenzi; Robert K. Brayton (DATE, 1999)

Probabilistic state space search. - Andreas Kuehlmann; Kenneth L. McMillan; Robert K. Brayton (ICCAD, 1999)

Timing-safe false path removal for combinational modules. - Yuji Kukimoto; Robert K. Brayton (ICCAD, 1999)

Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems. - Luca P. Carloni; Evguenii I. Goldberg; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI, 1999)

Multi-Valued Logic Synthesis. - Robert K. Brayton; Sunil P. Khatri (VLSI Design, 1999)

Sequential Multi-Valued Network Simplification using Redundancy Removal. - Sunil P. Khatri; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (VLSI Design, 1999)

Equivalences for Fair Kripke Structures. - Adnan Aziz; Felice Balarin; Vigyan Singhal; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (Chic. J. Theor. Comput. Sci., 1999)

Area and search space control for technology mapping. - Dirk-Jan Jongeneel; Yosinori Watanabe; Robert K. Brayton; Ralph H. J. M. Otten (DAC, 2000)

Don't Cares and Multi-Valued Logic Network Minimization. - Yunjian Jiang; Robert K. Brayton (ICCAD, 2000)

Cross-Talk Immune VLSI Design Using a Network of PLAs Embedded in a Regular Layout Fabric. - Sunil P. Khatri; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 2000)

A Force-Directed Macro-Cell Placer. - Fan Mo 003; Abdallah Tabbara; Robert K. Brayton (ICCAD, 2000)

Binary and Multi-Valued SPFD-Based Wire Removal in PLA Networks. - Subarnarekha Sinha; Sunil P. Khatri; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 2000)

Verification of Similar FSMs by Mixing Incremental Re-encoding, Reachability Analysis, and Combinational Checks. - Stefano Quer; Gianpiero Cabodi; Paolo Camurati; Luciano Lavagno; Ellen Sentovich; Robert K. Brayton (Formal Methods Syst. Des., 2000)

Performance planning. - Ralph H. J. M. Otten; Robert K. Brayton (Integr., 2000)

Integration of retiming with architectural floorplanning. - Abdallah Tabbara; Bassam Tabbara; Robert K. Brayton; A. Richard Newton (Integr., 2000)

Sequential synthesis using S1S. - Adnan Aziz; Felice Balarin; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Negative thinking in branch-and-bound: the case of unate covering. - Evguenii I. Goldberg; Luca P. Carloni; Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

Model-checking continous-time Markov chains. - Adnan Aziz; Kumud Sanwal; Vigyan Singhal; Robert K. Brayton (ACM Trans. Comput. Log., 2000)

Logic optimization and code generation for embedded control applications. - Yunjian Jiang; Robert K. Brayton (CODES, 2001)

Using SAT for combinational equivalence checking. - Evguenii I. Goldberg; Mukul R. Prasad; Robert K. Brayton (DATE, 2001)

Compatible Observability Don't Cares Revisited. - Robert K. Brayton (ICCAD, 2001)

A Force-Directed Maze Router. - Fan Mo 003; Abdallah Tabbara; Robert K. Brayton (ICCAD, 2001)

Sequential SPFDs. - Subarnarekha Sinha; Andreas Kuehlmann; Robert K. Brayton (ICCAD, 2001)

Solution of Parallel Language Equations for Logic Synthesis. - Nina Yevtushenko 001; Tiziano Villa; Robert K. Brayton; Alexandre Petrenko; Alberto L. Sangiovanni-Vincentelli (ICCAD, 2001)

A Timing-Driven Macro-Cell Placement Algorithm. - Fan Mo 003; Abdallah Tabbara; Robert K. Brayton (ICCD, 2001)

Partial-Order Reduction in Symbolic State-Space Exploration. - Rajeev Alur; Robert K. Brayton; Thomas A. Henzinger; Shaz Qadeer; Sriram K. Rajamani (Formal Methods Syst. Des., 2001)

Theory of safe replacements for sequential circuits. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

HW/SW partitioning and code generation of embedded control applications on a reconfigurable architecture platform. - Massimo Baleani; Frank Gennari; Yunjian Jiang; Yatish Patel; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (CODES, 2002)

Software synthesis from synchronous specifications using logic simulation techniques. - Yunjian Jiang; Robert K. Brayton (DAC, 2002)

River PLAs: a regular circuit structure. - Fan Mo 003; Robert K. Brayton (DAC, 2002)

Using Problem Symmetry in Search Based Satisfiability Algorithms. - Evguenii I. Goldberg; Mukul R. Prasad; Robert K. Brayton (DATE, 2002)

Whirlpool PLAs: a regular logic structure and their synthesis. - Fan Mo 003; Robert K. Brayton (ICCAD, 2002)

Optimization of Multi-Valued Multi-Level Networks. - Robert K. Brayton; M. Gao; Jie-Hong Roland Jiang; Yunjian Jiang; Yinghua Li; Alan Mishchenko; Subarnarekha Sinha; Tiziano Villa (ISMVL, 2002)

Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. - Yunjian Jiang; Robert K. Brayton (IWLS, 2002)

Reducing Multi-Valued Algebraic Operations to Binary. - Jie-Hong Roland Jiang; Alan Mishchenko; Robert K. Brayton (IWLS, 2002)

A Boolean Paradigm in Multi-Valued Logic Synthesis. - Alan Mishchenko; Robert K. Brayton (IWLS, 2002)

Simplification of Non-Deterministic Multi-Valued Networks. - Alan Mishchenko; Robert K. Brayton (IWLS, 2002)

Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. - Fan Mo 003; Robert K. Brayton (IWLS, 2002)

Topologically Constrained Logic Synthesis. - Subarnarekha Sinha; Alan Mishchenko; Robert K. Brayton (IWLS, 2002)

Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. - Nina Yevtushenko 001; Tiziano Villa; Robert K. Brayton; Alexandre Petrenko; Alberto L. Sangiovanni-Vincentelli (IWLS, 2002)

Formula-Dependent Equivalence for Compositional CTL Model Checking. - Adnan Aziz; Thomas R. Shiple; Vigyan Singhal; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (Formal Methods Syst. Des., 2002)

Don't cares in logic minimization of extended finite state machines. - Yunjian Jiang; Robert K. Brayton (ASP-DAC, 2003)

Generalized cofactoring for logic function evaluation. - Yunjian Jiang; Slobodan Matic; Robert K. Brayton (DAC, 2003)

A Theory of Non-Deterministic Networks. - Alan Mishchenko; Robert K. Brayton (ICCAD, 2003)

Fishbone: a block-level placement and routing scheme. - Fan Mo 003; Robert K. Brayton (ISPD, 2003)

On the verification of sequential equivalence. - Jie-Hong Roland Jiang; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

PLA-based regular structures and their synthesis. - Fan Mo 003; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Sequential optimization in the absence of global reset. - Vigyan Singhal; Carl Pixley; Adnan Aziz; Shaz Qadeer; Robert K. Brayton (ACM Trans. Design Autom. Electr. Syst., 2003)

Functional Dependency for Verification Reduction. - Jie-Hong Roland Jiang; Robert K. Brayton (CAV, 2004)

A timing-driven module-based chip design flow. - Fan Mo 003; Robert K. Brayton (DAC, 2004)

A new incremental placement algorithm and its application to congestion-aware divisor extraction. - Satrajit Chatterjee; Robert K. Brayton (ICCAD, 2004)

On breakable cyclic definitions. - Jie-Hong Roland Jiang; Alan Mishchenko; Robert K. Brayton (ICCAD, 2004)

SPFD-based wire removal in standard-cell and network-of-PLA circuits. - Sunil P. Khatri; Subarnarekha Sinha; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Gaining Predictability and Noise Immunity in Global Interconnects. - Yinghua Li; Alex Kondratyev; Robert K. Brayton (ACSD, 2005)

SAT-Based Complete Don't-Care Computation for Network Optimization. - Alan Mishchenko; Robert K. Brayton (DATE, 2005)

Efficient Solution of Language Equations Using Partitioned Representations. - Alan Mishchenko; Robert K. Brayton; Jie-Hong Roland Jiang; Tiziano Villa; Nina Yevtushenko 001 (DATE, 2005)

Synthesis methodology for built-in at-speed testing. - Yinghua Li; Alex Kondratyev; Robert K. Brayton (ICCAD, 2005)

DAG-aware AIG rewriting a fresh look at combinational logic synthesis. - Alan Mishchenko; Satrajit Chatterjee; Robert K. Brayton (DAC, 2006)

Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. - Jin S. Zhang; Alan Mishchenko; Robert K. Brayton; Malgorzata Chrzanowska-Jeske (DAC, 2006)

Factor cuts. - Satrajit Chatterjee; Alan Mishchenko; Robert K. Brayton (ICCAD, 2006)

Improvements to combinational equivalence checking. - Alan Mishchenko; Satrajit Chatterjee; Robert K. Brayton; Niklas Eén (ICCAD, 2006)

Reducing Structural Bias in Technology Mapping. - Satrajit Chatterjee; Alan Mishchenko; Robert K. Brayton; Xinning Wang; Timothy Kam (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Retiming and Resynthesis: A Complexity Perspective. - Jie-Hong Roland Jiang; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

A theory of nondeterministic networks. - Alan Mishchenko; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Using simulation and satisfiability to compute flexibilities in Boolean networks. - Alan Mishchenko; Jin S. Zhang; Subarnarekha Sinha; Jerry R. Burch; Robert K. Brayton; Malgorzata Chrzanowska-Jeske (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Automating Logic Rectification by Approximate SPFDs. - Yu-Shen Yang; Subarnarekha Sinha; Andreas G. Veneris; Robert K. Brayton (ASP-DAC, 2007)

On Resolution Proofs for Combinational Equivalence. - Satrajit Chatterjee; Alan Mishchenko; Robert K. Brayton; Andreas Kuehlmann (DAC, 2007)

Automated Extraction of Inductive Invariants to Aid Model Checking. - Michael L. Case; Alan Mishchenko; Robert K. Brayton (FMCAD, 2007)

Fast Minimum-Register Retiming via Binary Maximum-Flow. - Aaron P. Hurst; Alan Mishchenko; Robert K. Brayton (FMCAD, 2007)

A new algorithm for the largest compositionally progressive solution of synchronous language equations. - Tiziano Villa; Svetlana Zharikova; Nina Yevtushenko 001; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ACM Great Lakes Symposium on VLSI, 2007)

Combinational and sequential mapping with priority cuts. - Alan Mishchenko; Sungmin Cho; Satrajit Chatterjee; Robert K. Brayton (ICCAD, 2007)

A simultaneous bus orientation and bused pin flipping algorithm. - Fan Mo 003; Robert K. Brayton (ICCAD, 2007)

Semi-detailed bus routing with variation reduction. - Fan Mo 003; Robert K. Brayton (ISPD, 2007)

Improvements to Technology Mapping for LUT-Based FPGAs. - Alan Mishchenko; Satrajit Chatterjee; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Merging nodes under sequential observability. - Michael L. Case; Victor N. Kravets; Alan Mishchenko; Robert K. Brayton (DAC, 2008)

Scalable min-register retiming under timing and initializability constraints. - Aaron P. Hurst; Alan Mishchenko; Robert K. Brayton (DAC, 2008)

Invariant-Strengthened Elimination of Dependent State Elements. - Michael L. Case; Alan Mishchenko; Robert K. Brayton; Jason Baumgartner; Hari Mony (FMCAD, 2008)

Recording Synthesis History for Sequential Verification. - Alan Mishchenko; Robert K. Brayton (FMCAD, 2008)

Boolean factoring and decomposition of logic networks. - Alan Mishchenko; Robert K. Brayton; Satrajit Chatterjee (ICCAD, 2008)

Scalable and scalably-verifiable sequential synthesis. - Alan Mishchenko; Michael L. Case; Robert K. Brayton; Stephen Jang (ICCAD, 2008)

Placement based multiplier rewiring for cell-based designs. - Fan Mo 003; Robert K. Brayton (ICCAD, 2008)

Compositionally Progressive Solutions of Synchronous FSM Equations. - Nina Yevtushenko 001; Tiziano Villa; Robert K. Brayton; Alexandre Petrenko; Alberto L. Sangiovanni-Vincentelli (Discret. Event Dyn. Syst., 2008)

Speculative reduction-based scalable redundancy identification. - Hari Mony; Jason Baumgartner; Alan Mishchenko; Robert K. Brayton (DATE, 2009)

Sequential logic rectifications with approximate SPFDs. - Yu-Shen Yang; Subarna Sinha; Andreas G. Veneris; Robert K. Brayton; Duncan Exon Smith (DATE, 2009)

SmartOpt: an industrial strength framework for logic synthesis. - Stephen Jang; Dennis Wu; Mark Jarvin; Billy Chan; Kevin Chung; Alan Mishchenko; Robert K. Brayton (FPGA, 2009)

Synthesis of Multilevel Boolean Networks. - Tiziano Villa; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli; Yves Crama; Peter L. Hammer (Boolean Models and Methods, 2010)

ABC: An Academic Industrial-Strength Verification Tool. - Robert K. Brayton; Alan Mishchenko (CAV, 2010)

Combinational techniques for sequential equivalence checking. - Hamid Savoj; David Berthelot; Alan Mishchenko; Robert K. Brayton (FMCAD, 2010)

Global delay optimization using structural choices. - Alan Mishchenko; Robert K. Brayton; Stephen Jang (FPGA, 2010)

NSF Workshop on EDA: Past, Present, and Future (Part 1). - Robert K. Brayton; Jason Cong (IEEE Des. Test Comput., 2010)

NSF Workshop on EDA: Past, Present, and Future (Part 2). - Robert K. Brayton; Jason Cong (IEEE Des. Test Comput., 2010)

Efficient implementation of property directed reachability. - Niklas Eén; Alan Mishchenko; Robert K. Brayton (FMCAD, 2011)

Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. - Jiang Long; Sayak Ray; Baruch Sterin; Alan Mishchenko; Robert K. Brayton (DIFTS@FMCAD, 2011)

Delay optimization using SOP balancing. - Alan Mishchenko; Robert K. Brayton; Stephen Jang; Victor N. Kravets (ICCAD, 2011)

Automating Logic Transformations With Approximate SPFDs. - Yu-Shen Yang; Subarna Sinha; Andreas G. Veneris; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Scalable don't-care-based logic optimization and resynthesis. - Alan Mishchenko; Robert K. Brayton; Jie-Hong R. Jiang; Stephen Jang (ACM Trans. Reconfigurable Technol. Syst., 2011)

Scalable progress verification in credit-based flow-control systems. - Sayak Ray; Robert K. Brayton (DATE, 2012)

Mapping into LUT structures. - Sayak Ray; Alan Mishchenko; Niklas Eén; Robert K. Brayton; Stephen Jang; Chao Chen (DATE, 2012)

GLA: gate-level abstraction revisited. - Alan Mishchenko; Niklas Eén; Robert K. Brayton; Jason Baumgartner; Hari Mony; Pradeep Kumar Nalla (DATE, 2013)

A semi-canonical form for sequential AIGs. - Alan Mishchenko; Niklas Eén; Robert K. Brayton; Michael L. Case; Pankaj Chauhan; Nikhil Sharma (DATE, 2013)

LEC: Learning Driven Data-path Equivalence Checking. - Jiang Long; Robert K. Brayton; Michael L. Case (DIFTS@FMCAD, 2013)

Ranking structure in communication fabrics. - Sayak Ray; Robert K. Brayton (MEMOCODE, 2013)

ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. - Aadithya V. Karthik; Sayak Ray; Pierluigi Nuzzo; Alan Mishchenko; Robert K. Brayton; Jaijeet Roychowdhury (ASP-DAC, 2014)

NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). - Aadithya V. Karthik; David Soloveichik; Sayak Ray; Baruch Sterin; Alan Mishchenko; Robert K. Brayton; Jaijeet Roychowdhury (BCB, 2014)

Sequential Equivalence Checking for Clock-Gated Circuits. - Hamid Savoj; Alan Mishchenko; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Sequential equivalence checking of clock-gated circuits. - Yu-Yun Dai; Kei-Yong Khoo; Robert K. Brayton (DAC, 2015)

Bi-Decomposition Using Boolean Relations. - Anna Bernasconi 001; Robert K. Brayton; Valentina Ciriani; Gabriella Trucco; Tiziano Villa (DSD, 2015)

Simulation Graphs for Reverse Engineering. - Mathias Soeken; Baruch Sterin; Rolf Drechsler; Robert K. Brayton (FMCAD, 2015)

Technology Mapping into General Programmable Cells. - Alan Mishchenko; Robert K. Brayton; Wenyi Feng; Jonathan W. Greene (FPGA, 2015)

Automated Synthesis of Protocol Converters with BALM-II. - Giovanni Castagnetti; Matteo Piccolo; Tiziano Villa; Nina Yevtushenko 001; Robert K. Brayton; Alan Mishchenko (SEFM Workshops, 2015)

Design Automation of Electronic Systems: Past Accomplishments and Challenges Ahead [Scanning the Issue]. - Robert K. Brayton; Luca P. Carloni; Alberto L. Sangiovanni-Vincentelli; Tiziano Villa (Proc. IEEE, 2015)

Component-Based Design by Solving Language Equations. - Tiziano Villa; Alexandre Petrenko; Nina Yevtushenko 001; Alan Mishchenko; Robert K. Brayton (Proc. IEEE, 2015)

Efficient uninterpreted function abstraction and refinement for word-level model checking. - Yen-Sheng Ho; Pankaj Chauhan; Pritam Roy; Alan Mishchenko; Robert K. Brayton (FMCAD, 2016)

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. - Ana Petkovska; Alan Mishchenko; Mathias Soeken; Giovanni De Micheli; Robert K. Brayton; Paolo Ienne (ICCAD, 2016)

2QBF: Challenges and Solutions. - Valeriy Balabanov; Jie-Hong Roland Jiang; Christoph Scholl 001; Alan Mishchenko; Robert K. Brayton (SAT, 2016)

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. - Mathias Soeken; Alan Mishchenko; Ana Petkovska; Baruch Sterin; Paolo Ienne; Robert K. Brayton; Giovanni De Micheli (SAT, 2016)

m-Inductive Property of Sequential Circuits. - Hamid Savoj; Alan Mishchenko; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Fast-extract with cube hashing. - Bruno de O. Schmitt; Alan Mishchenko; Victor N. Kravets; Robert K. Brayton; André Inácio Reis (ASP-DAC, 2017)

Property directed reachability with word-level abstraction. - Yen-Sheng Ho; Alan Mishchenko; Robert K. Brayton (FMCAD, 2017)

Circuit recognition with deep learning. - Yu-Yun Dai; Robert K. Brayton (HOST, 2017)

Enabling exact delay synthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Pierre-Emmanuel Gaillardon; Janet Olson; Robert K. Brayton; Giovanni De Micheli (ICCAD, 2017)

Identifying Transparent Logic in Gate-Level Circuits. - Yu-Yun Dai; Robert K. Brayton (Advanced Logic Synthesis, 2018)

SAT-based area recovery in structural technology mapping. - Bruno de O. Schmitt; Alan Mishchenko; Robert K. Brayton (ASP-DAC, 2018)

Efficient computation of ECO patch functions. - Ai Quoc Dao; Nian-Ze Lee; Li-Cheng Chen; Mark Po-Hung Lin; Jie-Hong R. Jiang; Alan Mishchenko; Robert K. Brayton (DAC, 2018)

Canonical computation without canonical representation. - Alan Mishchenko; Robert K. Brayton; Ana Petkovska; Mathias Soeken; Luca G. Amarù; Antun Domic (DAC, 2018)

Improvements to boolean resynthesis. - Luca Gaetano Amarù; Mathias Soeken; Patrick Vuillod; Jiong Luo; Alan Mishchenko; Janet Olson; Robert K. Brayton; Giovanni De Micheli (DATE, 2018)

Practical exact synthesis. - Mathias Soeken; Winston Haaswijk; Eleonora Testa; Alan Mishchenko; Luca Gaetano Amarù; Robert K. Brayton; Giovanni De Micheli (DATE, 2018)

Verification and Synthesis of Clock-Gated Circuits. - Yu-Yun Dai; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Simulation-Guided Boolean Resubstitution. - Siang-Yun Lee; Heinz Riener; Alan Mishchenko; Robert K. Brayton; Giovanni De Micheli (CoRR, 2020)

Deep Integration of Circuit Simulator and SAT Solver. - He-Teng Zhang; Jie-Hong R. Jiang; Luca G. Amarù; Alan Mishchenko; Robert K. Brayton (DAC, 2021)

A Simulation-Guided Paradigm for Logic Synthesis and Verification. - Siang-Yun Lee; Heinz Riener; Alan Mishchenko; Robert K. Brayton; Giovanni De Micheli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Practical Boolean Decomposition for Delay-driven LUT Mapping. - Alessandro Tempia Calvino; Alan Mishchenko; Giovanni De Micheli; Robert K. Brayton (CoRR, 2024)

Enhancing Delay-Driven LUT Mapping With Boolean Decomposition. - Alessandro Tempia Calvino; Giovanni De Micheli; Alan Mishchenko; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)