80Kb 10ns read cycle logic Embedded High-K charge trap Multi-Time-Programmable Memory scalable to 14nm FIN with no added process complexity. - Janakiraman Viraraghavan; Derek Leu; Balaji Jayaraman; Alberto Cestero; Robert Kilker; Ming Yin; John Golz; Rajesh Reddy Tummuru; Ramesh Raghavan; Dan Moy; Thejas Kempanna; Faraz Khan; et al. (VLSI Circuits, 2016)