Modelling Peripheral Designs using FSM-like Notation for Complete Property Set Generation. - Endri Kaja; Nicolas Gerlin; Robert Kunzelmann; Keerthikumara Devarajegowda; Wolfgang Ecker (MCSoC, 2023)

Effective Processor Model Generation from Instruction Set Simulator to Hardware Design. - Johannes Kappes; Robert Kunzelmann; Karsten Emrich; Conrad Foik; Daniel Mueller-Gritschneder; Wolfgang Ecker (NorCAS, 2023)

CPU to FPGA Power Covert Channel in FPGA-SoCs. - Mathieu Gross; Robert Kunzelmann; Georg Sigl (IACR Cryptol. ePrint Arch., 2023)

Fake Timer: An Engine for Accurate Timing Estimation in Register Transfer Level Designs. - Daniela Sanchez Lopera; Robert Kunzelmann; Endri Kaja; Wolfgang Ecker (ISQED, 2024)

Leveraging Large Language Models for the Automated Documentation of Hardware Designs. - Saruni Fernando; Robert Kunzelmann; Daniela Sanchez Lopera; Jad Al Halabi; Wolfgang Ecker (MECO, 2024)

The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages. - Johannes Schreiner; Daniel Gerl; Robert Kunzelmann; Paritosh Kumar Sinha; Wolfgang Ecker (CoRR, 2024)

Flexible Generation of Fast and Accurate Software Performance Simulators From Compact Processor Descriptions. - Conrad Foik; Robert Kunzelmann; Daniel Mueller-Gritschneder; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Implementation of Dynamic SISD-SIMD Integer Dividers. - Gianluca Radi; Ares Tahiraga; Robert Kunzelmann; Ties Jan Henderikus Kluter; Wolfgang Ecker (DDECS, 2025)

Execute Your Darlings: Dynamic Execution of High-Level Formal Specifications for Validation and Early Prototyping. - Robert Kunzelmann; Zeyad Tahoun; Wolfgang Ecker (RAPIDO@HiPEAC, 2025)