Digital delay line clock shapers and multipliers. - Roland A. Bechade; Robert M. Houle (IBM J. Res. Dev., 1995)

Simple Statistical Analysis Techniques to Determine Minimum Sense Amp Set Times. - Robert M. Houle (CICC, 2007)

Simple Statistical Analysis Techniques to Determine Optimum Sense Amp Set Times. - Robert M. Houle (IEEE J. Solid State Circuits, 2008)

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Frank Pavlik; Adnan Seferagic; Liang-Yu Chen; Shang-Bin Ko; Carl Radens (ISSCC, 2011)

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements. - Harold Pilo; Igor Arsovski; Kevin Batson; Geordie Braceras; John A. Gabric; Robert M. Houle; Steve Lamphier; Carl Radens; Adnan Seferagic (IEEE J. Solid State Circuits, 2012)

A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction. - Harold Pilo; Chad A. Adams; Igor Arsovski; Robert M. Houle; Steve Lamphier; Michael M. Lee; Frank Pavlik; Sushma N. Sambatur; Adnan Seferagic; Richard Wu; Mohammad Imran Younus (ISSCC, 2013)

12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. - Igor Arsovski; Michael Fragano; Robert M. Houle; Akhilesh Patil; Van Butler; Raymond Kim; Ramon Rodriguez; Tom Maffitt; Joseph J. Oler; John Goss; Christopher Parkinson; Michael A. Ziegerhofer; et al. (ISSCC, 2017)

1.4Gsearch/s 2-Mb/mm2 TCAM Using Two-Phase-Pre-Charge ML Sensing and Power-Grid Pre-Conditioning to Reduce Ldi/dt Power-Supply Noise by 50%. - Igor Arsovski; Akhilesh Patil; Robert M. Houle; Michael Fragano; Ramon Rodriguez; Raymond Kim; Van Butler (IEEE J. Solid State Circuits, 2018)