Increasing the number of effective registers in a low-power processor using a windowed register file. - Rajiv A. Ravindran; Robert M. Senger; Eric D. Marsman; Ganesh S. Dasika; Matthew R. Guthaus; Scott A. Mahlke; Richard B. Brown (CASES, 2003)

A 16-bit mixed-signal microsystem with integrated CMOS-MEMS clock reference. - Robert M. Senger; Eric D. Marsman; Michael S. McCorquodale; Fadi H. Gebara; Keith L. Kraver; Matthew R. Guthaus; Richard B. Brown (DAC, 2003)

A Top-Down Microsystems Design Methodology and Associated Challenges . - Michael S. McCorquodale; Fadi H. Gebara; Keith L. Kraver; Eric D. Marsman; Robert M. Senger; Richard B. Brown (DATE, 2003)

Microsystem and SoC Design with UMIPS. - Michael S. McCorquodale; Eric D. Marsman; Robert M. Senger; Fadi H. Gebara; Richard B. Brown (VLSI-SOC, 2003)

Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache. - Rajiv A. Ravindran; Pracheeti D. Nagarkar; Ganesh S. Dasika; Eric D. Marsman; Robert M. Senger; Scott A. Mahlke; Richard B. Brown (CGO, 2005)

A 16-bit low-power microcontroller with monolithic MEMS-LC clocking. - Robert M. Senger; Eric D. Marsman; Michael S. McCorquodale (ISCAS (1), 2005)

Partitioning Variables across Register Windows to Reduce Spill Code in a Low-Power Processor. - Rajiv A. Ravindran; Robert M. Senger; Eric D. Marsman; Ganesh S. Dasika; Matthew R. Guthaus; Scott A. Mahlke; Richard B. Brown (IEEE Trans. Computers, 2005)

A 16-bit, low-power microsystem with monolithic MEMS-LC clocking. - Robert M. Senger; Eric D. Marsman; Michael S. McCorquodale; Richard B. Brown (ASP-DAC, 2006)

DSP architecture for cochlear implants. - Eric D. Marsman; Robert M. Senger; Gordy A. Carichner; Sundus Kubba; Michael S. McCorquodale; Richard B. Brown (ISCAS, 2006)

Low-latency, HDL-synthesizable dynamic clock frequency controller with self-referenced hybrid clocking. - Robert M. Senger; Eric D. Marsman; Gordy A. Carichner; Sundus Kubba; Michael S. McCorquodale; Richard B. Brown (ISCAS, 2006)

A dual-VDD boosted pulsed bus technique for low power and low leakage operation. - Harmander Deogun; Robert M. Senger; Dennis Sylvester; Richard B. Brown; Kevin J. Nowka (ISLPED, 2006)

A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. - Alan J. Drake; Robert M. Senger; Harmander Deogun; Gary D. Carpenter; Soraya Ghiasi; Tuyet Nguyen; Norman K. James; Michael S. Floyd; Vikas Pokala (ISSCC, 2007)

The IBM Blue Gene/Q interconnection network and message unit. - Dong Chen 005; Noel Eisley; Philip Heidelberger; Robert M. Senger; Yutaka Sugawara; Sameer Kumar 001; Valentina Salapura; David L. Satterfield; Burkhard D. Steinmacher-Burow; Jeffrey J. Parker (SC, 2011)

Looking under the hood of the IBM blue gene/Q network. - Dong Chen 005; Noel Eisley; Philip Heidelberger; Sameer Kumar 001; Amith R. Mamidala; Fabrizio Petrini; Robert M. Senger; Yutaka Sugawara; Robert Walkup; Burkhard D. Steinmacher-Burow; Anamitra R. Choudhury; Yogish Sabharwal; et al. (SC, 2012)

The IBM Blue Gene/Q Interconnection Fabric. - Dong Chen 005; Noel Eisley; Philip Heidelberger; Robert M. Senger; Yutaka Sugawara; Sameer Kumar 001; Valentina Salapura; David L. Satterfield; Burkhard D. Steinmacher-Burow; Jeffrey J. Parker (IEEE Micro, 2012)

Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor. - Alan J. Drake; Michael S. Floyd; Richard L. Willaman; Derek J. Hathaway; Joshua Hernandez; Crystal Soja; Marshall D. Tiner; Gary D. Carpenter; Robert M. Senger (ISLPED, 2013)

Soft Error Resiliency Characterization on IBM BlueGene/Q Processor. - Chen-Yong Cher; K. Paul Muller; Ruud A. Haring; David L. Satterfield; Thomas E. Musta; Thomas Gooding; Kristan D. Davis; Marc Boris Dombrowa; Gerard V. Kopcsay; Robert M. Senger; Yutaka Sugawara; Krishnan Sugavanam (ASP-DAC, 2014)

Soft error resiliency characterization and improvement on IBM BlueGene/Q processor using accelerated proton irradiation. - Chen-Yong Cher; K. Paul Muller; Ruud A. Haring; David L. Satterfield; Thomas E. Musta; Thomas Gooding; Kristan D. Davis; Marc Boris Dombrowa; Gerard V. Kopcsay; Robert M. Senger; Yutaka Sugawara; Krishnan Sugavanam (ITC, 2014)

Data Movement Accelerator Engines on a Prototype Power10 Processor. - Yutaka Sugawara; Dong Chen 005; Ruud A. Haring; Abdullah Kayi; Eugene Ratzlaff; Robert M. Senger; Krishnan Sugavanam; Ralph Bellofatto; Ben J. Nathanson; Craig B. Stunkel (IEEE Micro, 2023)

14.1 A Software-Assisted Peak Current Regulation Scheme to Improve Power-Limited Inference Performance in a 5nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (ISSCC, 2024)

Power-Limited Inference Performance Optimization Using a Software-Assisted Peak Current Regulation Scheme in a 5-nm AI SoC. - Monodeep Kar; Joel Silberman; Swagath Venkataramani; Viji Srinivasan; Bruce M. Fleischer; Joshua Rubin; JohnDavid Lancaster; Sae Kyu Lee; Matthew Cohen; Matthew M. Ziegler; Nianzheng Cao; Sandra Woodward; et al. (IEEE J. Solid State Circuits, 2025)