A Generic Architecture for Robust Asynchronous Communication Links. - Jakob Lechner; Robert Najvirt (PATMOS, 2012)

Classifying Virtual Channel Access Control Schemes for Asynchronous NoCs. - Robert Najvirt; Syed Rameez Naqvi; Andreas Steininger (ASYNC, 2013)

A Multi-Credit Flow Control scheme for asynchronous NoCs. - Syed Rameez Naqvi; Robert Najvirt; Andreas Steininger (DDECS, 2013)

Equivalence of clock gating and synchronization with applicability to GALS communication. - Robert Najvirt; Andreas Steininger (PATMOS, 2014)

Faithful Glitch Propagation in Binary Circuit Models. - Matthias Függer; Robert Najvirt; Thomas Nowak; Ulrich Schmid 001 (CoRR, 2014)

How to Synchronize a Pausible Clock to a Reference. - Robert Najvirt; Andreas Steininger (ASYNC, 2015)

Towards binary circuit models that faithfully capture physical solvability. - Matthias Függer; Robert Najvirt; Thomas Nowak; Ulrich Schmid 001 (DATE, 2015)

Containment of Metastable Voltages in FPGAs. - Robert Najvirt; Thomas Polzer; Florian Beck; Andreas Steininger (DDECS, 2015)

A pausible clock with crystal oscillator accuracy. - Robert Najvirt; Andreas Steininger (ECCTD, 2015)

Experimental Validation of a Faithful Binary Circuit Model. - Robert Najvirt; Ulrich Schmid 001; Michael Hofbauer; Matthias Függer; Thomas Nowak; Kurt Schweiger (ACM Great Lakes Symposium on VLSI, 2015)

A versatile and reliable glitch filter for clocks. - Robert Najvirt; Andreas Steininger (PATMOS, 2015)

The Metastable Behavior of a Schmitt-Trigger. - Andreas Steininger; Jürgen Maier 002; Robert Najvirt (ASYNC, 2016)

Does Cascading Schmitt-Trigger Stages Improve the Metastable Behavior? - Andreas Steininger; Robert Najvirt; Jürgen Maier 002 (DSD, 2016)

On the Appropriate Handling of Metastable Voltages in FPGAs. - Thomas Polzer; Robert Najvirt; Florian Beck; Andreas Steininger (J. Circuits Syst. Comput., 2016)

Measuring Metastability with Free-Running Clocks. - Robert Najvirt; Thomas Polzer; Andreas Steininger (ASYNC, 2017)

A faithful binary circuit model with adversarial noise. - Matthias Függer; Jürgen Maier 002; Robert Najvirt; Thomas Nowak; Ulrich Schmid 001 (DATE, 2018)

A Faithful Binary Circuit Model. - Matthias Függer; Robert Najvirt; Thomas Nowak; Ulrich Schmid 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Towards Explaining the Fault Sensitivity of Different QDI Pipeline Styles. - Patrick Behal; Florian Huemer; Robert Najvirt; Andreas Steininger; Zaheer Tabassam (ASYNC, 2021)

An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital Circuits. - Patrick Behal; Florian Huemer; Robert Najvirt; Andreas Steininger (DSD, 2021)

On SAT-Based Model Checking of Speed-Independent Circuits. - Florian Huemer; Robert Najvirt; Andreas Steininger (DDECS, 2022)

ζ: A Novel Approach for Mitigating Single Event Transient Effects in Quasi Delay Insensitive Logic. - Zaheer Tabassam; Andreas Steininger; Robert Najvirt; Florian Huemer (ASYNC, 2023)

The Hidden Behavior of a D-Latch. - Jürgen Maier 002; Andreas Steininger; Robert Najvirt (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)