High-density central I/O circuits for CMOS. - Robert P. Masleid (IEEE J. Solid State Circuits, 1991)

The next-generation 64b SPARC core in a T4 SoC processor. - Jinuk Luke Shin; Heechoul Park; Hongping Penny Li; Alan P. Smith 002; Youngmoon Choi; Harikaran Sathianathan; Sudesna Dash; Sebastian Turullols; Song Kim; Robert P. Masleid; Georgios K. Konstadinidis; Robert T. Golla; et al. (ISSCC, 2012)

3.6GHz 16-core SPARC SoC processor in 28nm. - Jason Hart; Steve Butler; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Lance Kwong; Robert P. Masleid; et al. (ISSCC, 2013)

The Next Generation 64b SPARC Core in a T4 SoC Processor. - Jinuk Luke Shin; Robert T. Golla; Hongping Penny Li; Sudesna Dash; Youngmoon Choi; Alan P. Smith 002; Harikaran Sathianathan; Mayur Joshi; Heechoul Park; Mohamed Elgebaly; Sebastian Turullols; Song Kim; et al. (IEEE J. Solid State Circuits, 2013)

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. - Jason Hart; Hoyeol Cho; Yuefei Ge; Gregory Gruber; Dawei Huang; Changku Hwang; Daisy Jian; Timothy Johnson; Georgios K. Konstadinidis; Venkatram Krishnaswamy; Lance Kwong; Robert P. Masleid; et al. (IEEE J. Solid State Circuits, 2014)

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. - Penny Li; Jinuk Luke Shin; Georgios K. Konstadinidis; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; et al. (ISSCC, 2015)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)