Online digital computer measurement of a neurological control system. - Lawrence Stark; Robert Payne; Yutaka Okabe (Commun. ACM, 1962)

Self-timed field programmmable gate array architectures. - Robert Payne (1997)

Panel: What is the Proper System on Chip Design Methodology. - Richard Goering; Pierre Bricaud; James G. Dougherty; Steve Glaser; Michael Keating; Robert Payne; Davoud Samani (DAC, 1999)

A 6.25-Gb/s binary transceiver in 0.13-μm CMOS for serial data transmission across high loss legacy backplane channels. - Robert Payne; Paul E. Landman; Bhavesh Bhakta; Sridhar Ramaswamy; Song Wu; John D. Powers; M. Ulvi Erdogan; Ah-Lyan Yee; Richard Gu; Lin Wu; Yiqun Xie; Bharadwaj Parthasarathy; et al. (IEEE J. Solid State Circuits, 2005)

Multi-GB/s Transceivers. - Robert Payne; Muneo Fukaishi (ISSCC, 2007)

Future of High-Speed Transceivers (Forum). - Robert Payne (ISSCC, 2008)

A 18mW 10Gbps continuous-time FIR equalizer for wired line data communications in 0.12µm CMOS. - Hao Liu; Jin Liu 004; Robert Payne; Cy Cantrell; Mark Morgan (CICC, 2009)

Will ADCs overtake binary frontends in backplane signaling? - Ali Sheikholeslami; Robert Payne (ISSCC, 2009)

A 16b 100-to-160MS/s SiGe BiCMOS pipelined ADC with 100dBFS SFDR. - Robert Payne; Marco Corsi; David Smith; Scott Kaylor; Daniel Hsieh (ISSCC, 2010)

Energy-efficient high-speed interfaces. - Naresh R. Shanbhag; Koichi Yamaguchi; Robert Payne (ISSCC, 2010)

A 16-Bit 100 to 160 MS/s SiGe BiCMOS Pipelined ADC With 100 dBFS SFDR. - Robert Payne; Marco Corsi; David Smith; Tien-Ling Hsieh; Scott Kaylor (IEEE J. Solid State Circuits, 2010)

Good, bad, ugly - 20 years of broadband evolution: What's next? - Jerry Lin; Franz Dielacher; Jing-Hong Conan Zhan; Robert Payne (ISSCC, 2011)

A 12b 1GS/s SiGe BiCMOS two-way time-interleaved pipeline ADC. - Robert Payne; Charles K. Sestok; William Bright; Manar El-Chammas; Marco Corsi; David Smith; Noam Tal (ISSCC, 2011)

Session 7 overview: Multi-Gb/s receiver and parallel I/O techniques: Wireline subcommittee. - Robert Payne; Tatsuya Saito (ISSCC, 2012)

A 10GS/s 6b time-interleaved ADC with partially active flash sub-ADCs. - Xiaochen Yang; Robert Payne; Jin Liu 004 (CICC, 2013)

A 5-Gb/s Automatic Sub-Bit Between-Pair Skew Compensator for Parallel Data Communications in 0.13-µm CMOS. - Yuxiang Zheng; Jin Liu 004; Robert Payne; Mark Morgan; Hoi Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 12 Bit 1.6 GS/s BiCMOS 2×2 Hierarchical Time-Interleaved Pipeline ADC. - Manar El-Chammas; Xiaopeng Li; Shigenobu Kimura; Kenneth Maclean; Jake Hu; Mark Weaver; Matthew Gindlesperger; Scott Kaylor; Robert Payne; Charles K. Sestok; William Bright (IEEE J. Solid State Circuits, 2014)

An efficient and resilient ultra-high speed galvanic data isolator leveraging broad-band multi resonant tank electro-magnetic coupling. - Swaminathan Sankaran; Bradley Kramer; Gregory Howard; Benjamin Sutton; Randall Walberg; Vijaylaxmi Khanolkar; Robert Payne; Mark Morgan (VLSIC, 2015)

A Sub-THz CMOS Transceiver IC and System for Medium-Reach Guided Wave and Short-Reach Wireless Communication Links. - Swaminathan Sankaran; Gerd Schuppener; Juan Herbsommer; Bradley Kramer; Hassan Ali; Robert Payne; Carole Rush; Baher Haroun; Nirmal Warke (MWSCAS, 2024)