A 10-mW two-channel fully integrated system-on-chip for eddy-current position sensing [in biomedical devices]. - Michael Oberle; Robert Reutemann; Jürgen Hertle; Qiuting Huang (IEEE J. Solid State Circuits, 2002)

A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. - Thomas Toifl; Christian Menolfi; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Robert Reutemann; Michael Ruegg; Martin L. Schmatz; Jonas R. M. Weiss (IEEE J. Solid State Circuits, 2005)

A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Jonas R. M. Weiss; Martin L. Schmatz (IEEE J. Solid State Circuits, 2006)

A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End. - Chiara Martelli; Robert Reutemann; Christian Benkeser; Qiuting Huang (ISSCC, 2007)

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (ISSCC, 2010)

A 4.5 mW/Gb/s 6.4 Gb/s 22+1-Lane Source Synchronous Receiver Core With Optional Cleanup PLL in 65 nm CMOS. - Robert Reutemann; Michael Ruegg; Fran Keyser; John Bergkvist; Daniel Dreps; Thomas Toifl; Martin L. Schmatz (IEEE J. Solid State Circuits, 2010)

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Daniel Dreps; Troy J. Beukema; Andrea Prati 002; Daniele Gardellini; Marcel A. Kossel; Peter Buchmann; Matthias Braendli; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2012)

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Troy J. Beukema; William R. Kelly; Hui H. Xu; David Freitas; Andrea Prati 002; Daniele Gardellini; Robert Reutemann; Giovanni Cervelli; Juergen Hertle; et al. (IEEE J. Solid State Circuits, 2014)