A Glitch-Free Single-Phase CMOS DFF for Gigahertz Applications. - Qiuting Huang; Robert Rogenmoser (ISCAS, 1994)

Stochastic Methods for Transistor Size Optimization of CMOS VLSI Circuits. - Robert Rogenmoser; Hubert Kaeslin; Tobias Blickle (PPSN, 1996)

Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks. - Qiuting Huang; Robert Rogenmoser (IEEE J. Solid State Circuits, 1996)

An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops. - Robert Rogenmoser; Qiuting Huang (IEEE J. Solid State Circuits, 1996)

The impact of transistor sizing on power efficiency in submicron CMOS circuits. - Robert Rogenmoser; Hubert Kaeslin (IEEE J. Solid State Circuits, 1997)

A 2× load/store pipe for a low-power 1-GHz embedded processor. - Zongjian Chen; Daniel Murray; Steve Nishimoto; Mark H. Pearce; Max Oyker; Daniel Rodriguez; Robert Rogenmoser; Dongwook (Drew) Suh; Erik Supnet; Vincent von Kaenel; George Yiu (IEEE J. Solid State Circuits, 2003)

LVS verification across multiple power domains for a quad-core microprocessor. - Wei Li; Daniel Blakely; Scott Van Sooy; Keven Dunn; David Kidd; Robert Rogenmoser; Dian Zhou (ACM Trans. Design Autom. Electr. Syst., 2006)

Reducing transistor variability for high performance low power chips. - Robert Rogenmoser (Hot Chips Symposium, 2012)

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. - Vineet Agrawal; N. Kepler; David Kidd; Gokul Krishnan; Samuel Leshner; T. Bakishev; D. Zhao; P. Ranade; R. Roy; M. Wojko; Lawrence T. Clark; Robert Rogenmoser; et al. (CICC, 2013)

A slew-rate based process monitor and bi-directional body bias circuit for adaptive body biasing in SoC applications. - Sang-Soo Lee; Edward Boling; Augustine Kuo; Robert Rogenmoser (CICC, 2013)

Reducing Transistor Variability for High Performance Low Power Chips. - Robert Rogenmoser; Lawrence T. Clark (IEEE Micro, 2013)