A cascaded continuous-time ΣΔ Modulator with 67-dB dynamic range in 10-MHz bandwidth. - Lucien J. Breems; Robert Rutten; Gunnar Wetzker (IEEE J. Solid State Circuits, 2004)

Continuous-time Sigma-Delta Modulators for Highly Digitised Receivers. - Lucien J. Breems; Robert H. M. van Veldhoven; Kathleen Philips; Robert Rutten; Gunnar Wetzker (ICECS, 2006)

A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band. - Lucien J. Breems; Robert Rutten; Robert H. M. van Veldhoven; Gerard van der Weide; Henk A. H. Termeer (ISSCC, 2007)

A 56 mW Continuous-Time Quadrature Cascaded ΣΔ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band. - Lucien J. Breems; Robert Rutten; Robert H. M. van Veldhoven; Gerard van der Weide (IEEE J. Solid State Circuits, 2007)

Digital jitter-cancellation for narrowband signals. - Robert Rutten; Lucien J. Breems; Robert H. M. van Veldhoven (ISCAS, 2008)

An Inverter-Based Hybrid ΔΣ Modulator. - Robert H. M. van Veldhoven; Robert Rutten; Lucien J. Breems (ISSCC, 2008)

A 45nm WCDMA transmitter using direct quadrature voltage modulator with high oversampling digital front-end. - Xin He; Jan van Sinderen; Robert Rutten (ISSCC, 2010)

A 4GHz CT ΔΣ ADC with 70dB DR and -74dBFS THD in 125MHz BW. - Muhammed Bolatkale; Lucien J. Breems; Robert Rutten; Kofi A. A. Makinwa (ISSCC, 2011)

A 4 GHz Continuous-Time ΔΣ ADC With 70 dB DR and -74 dBFS THD in 125 MHz BW. - Muhammed Bolatkale; Lucien J. Breems; Robert Rutten; Kofi A. A. Makinwa (IEEE J. Solid State Circuits, 2011)

A 6.5 GHz Arbitrary Digital Waveform Generator. - Frank Leong; Robert Rutten; Nenad Pavlovic; Amine Mounaim (ESSCIRC, 2012)

Wideband UHF ISM-band transceiver supporting multichannel reception and DSSS modulation. - Jan van Sinderen; Gerben W. de Jong; Frank Leong; Xin He; Melina Apostolidou; Harish Kundur Subramaniyan; Robert Rutten; Jan Niehof; Jos Verlinden; Hao Wang; Anton Hoogstraate; Ka Chun Kwok; et al. (ISSCC, 2013)

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain using Carry-Save format numbers. - Yanxiang Huang; Ajay Kapoor; Robert Rutten; José Pineda de Gyvez (NORCHIP, 2013)

A 13 bits 4.096 GHz 45 nm CMOS digital decimation filter chain with Carry-Save format numbers. - Yanxiang Huang; Ajay Kapoor; Robert Rutten; José Pineda de Gyvez (Microprocess. Microsystems, 2015)

15.2 A 2.2GHz continuous-time ΔΣ ADC with -102dBc THD and 25MHz BW. - Lucien J. Breems; Muhammed Bolatkale; Hans Brekelmans; Shagun Bajoria; Jan Niehof; Robert Rutten; Bert Oude-Essink; Franco Fritschij; Jagdip Singh; Gerard Lassche (ISSCC, 2016)

A 2.2 GHz Continuous-Time ΔΣ ADC With -102 dBc THD and 25 MHz Bandwidth. - Lucien J. Breems; Muhammed Bolatkale; Hans Brekelmans; Shagun Bajoria; Jan Niehof; Robert Rutten; Bert Oude-Essink; Franco Fritschij; Jagdip Singh; Gerard Lassche (IEEE J. Solid State Circuits, 2016)

A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator. - Pierluigi Cenci; Muhammed Bolatkale; Robert Rutten; Gerard Lassche; Kofi A. A. Makinwa; Lucien J. Breems (ESSCIRC, 2017)

A 3.2mW SAR-assisted CTΔ∑ ADC with 77.5dB SNDR and 40MHz BW in 28nm CMOS. - Pierluigi Cenci; Muhammed Bolatkale; Robert Rutten; M. Ganzerli; Gerard Lassche; Kofi A. A. Makinwa; Lucien J. Breems (VLSI Circuits, 2019)

A 6GS/s 0.5GHz BW continuous-time 2-1-1 MASH ΔΣ modulator with phase-boosted current-mode ELD compensation in 40nm CMOS. - Chenming Zhang; Lucien J. Breems; Qilong Liu; Georgi I. Radulov; Muhammed Bolatkale; Shagun Bajoria; Robert Rutten; Arthur H. M. van Roermund (ESSCIRC, 2021)

A 2GHz 2-bit Continuous-Time Delta Sigma ADC with 2GHz chopper achieving 12nV/sqrt(Hz) 1/f noise at 153kHz and -104.7dBc THD in 30MHz BW. - Pierluigi Cenci; Hans Brekelmans; Shagun Bajoria; Marcello Ganzerli; Bernard Burdiek; Robert Rutten; Yihan Gao; Muhammed Bolatkale; Paul Swinkels; Lucien J. Breems (ESSCIRC, 2022)

A 28nm 6GHz 2b Continuous-Time ΔΣ ADC with -101 dBc THD and 120MHz Bandwidth Using Digital DAC Error Correction. - Muhammed Bolatkale; Robert Rutten; Hans Brekelmans; Shagun Bajoria; Yihan Gao; Bernard Burdiek; Lucien J. Breems (ISSCC, 2022)

A 5GS/s 360MHz-BW 68dB-DR Continuous-Time 1-1-1 Filtering MASH ΔΣ ADC in 40nm CMOS. - Qilong Liu; Lucien J. Breems; Chenming Zhang; Shagun Bajoria; Muhammed Bolatkale; Robert Rutten; Georgi I. Radulov (ISSCC, 2022)

A 28-nm 6-GHz 2-bit Continuous-Time ΔΣ ADC With -101-dBc THD and 120-MHz Bandwidth Using Blind Digital DAC Error Correction. - Muhammed Bolatkale; Robert Rutten; Hans Brekelmans; Shagun Bajoria; Yihan Gao; Bernard Burdiek; Lucien J. Breems (IEEE J. Solid State Circuits, 2022)

A 158-mW 360-MHz BW 68-dB DR Continuous-Time 1-1-1 Filtering MASH ADC in 40-nm CMOS. - Qilong Liu; Lucien J. Breems; Shagun Bajoria; Muhammed Bolatkale; Robert Rutten; Georgi I. Radulov (IEEE J. Solid State Circuits, 2022)

A 6GHz Multi-Path Multi-Frequency Chopping CTΔΣ Modulator achieving 122dBFS SFDR from 150kHz to 120MHz BW. - Sundeep Javvaji; Muhammed Bolatkale; Shagun Bajoria; Robert Rutten; Bert Oude-Essink; Koen Beijens; Kofi A. A. Makinwa; Lucien J. Breems (VLSI Technology and Circuits, 2023)

A 120-MHz BW, 122-dBFS SFDR CTΔΣ ADC With a Multi-Path Multi-Frequency Chopping Scheme. - Sundeep Javvaji; Muhammed Bolatkale; Shagun Bajoria; Robert Rutten; Bert Oude-Essink; Koen Beijens; Kofi A. A. Makinwa; Lucien J. Breems (IEEE J. Solid State Circuits, 2024)

Quantization Noise Cancellation Through Modelling of Non-Linearities in Sigma Delta Modulators. - Stijn Ringeling; Marco Fattori; Shagun Bajoria; Robert Rutten; Lucien J. Breems; Eugenio Cantatore (ISCAS, 2025)

A 6-GHz Continuous-Time Bandpass ΔΣ ADC With Background Filter Calibration and -100 dBc IM3 for a Mixer-Less DAB Band III Receiver. - Shagun Bajoria; Robert Rutten; Muhammed Bolatkale; Yihan Gao; Hans Brekelmans; Bernard Burdiek; Hendrik van der Ploeg; Lucien J. Breems (IEEE J. Solid State Circuits, 2025)