Performance- and value-oriented decision support for supply chain configuration. - Marcus Brandenburg; Heinrich Kuhn; Robert Schilling; Stefan Seuring (Logist. Res., 2014)

Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS. - Frank K. Gürkaynak; Robert Schilling; Michael Muehlberghuber; Francesco Conti 001; Stefan Mangard; Luca Benini (CS2@HiPEAC, 2017)

Leakage Bounds for Gaussian Side Channels. - Thomas Unterluggauer; Thomas Korak; Stefan Mangard; Robert Schilling; Luca Benini; Frank K. Gürkaynak; Michael Muehlberghuber (IACR Cryptol. ePrint Arch., 2017)

Transparent Memory Encryption and Authentication. - Mario Werner; Thomas Unterluggauer; Robert Schilling; David Schaffenrath; Stefan Mangard (IACR Cryptol. ePrint Arch., 2017)

An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. - Francesco Conti 001; Robert Schilling; Pasquale Davide Schiavone; Antonio Pullini; Davide Rossi; Frank Kagan Gürkaynak; Michael Muehlberghuber; Michael Gautschi; Igor Loi; Germain Haugou; Stefan Mangard; Luca Benini (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Pointing in the Right Direction - Securing Memory Accesses in a Faulty World. - Robert Schilling; Mario Werner; Pascal Nasahl; Stefan Mangard (ACSAC, 2018)

High speed ASIC implementations of leakage-resilient cryptography. - Robert Schilling; Thomas Unterluggauer; Stefan Mangard; Frank K. Gürkaynak; Michael Muehlberghuber; Luca Benini (DATE, 2018)

Securing conditional branches in the presence of fault attacks. - Robert Schilling; Mario Werner; Stefan Mangard (DATE, 2018)

Protecting RISC-V Processors against Physical Attacks. - Mario Werner; Robert Schilling; Thomas Unterluggauer; Stefan Mangard (DATE, 2019)

Small Faults Grow Up - Verification of Error Masking Robustness in Arithmetically Encoded Programs. - Anja F. Karl; Robert Schilling; Roderick Bloem; Stefan Mangard (VMCAI, 2019)

ConTExT: Leakage-Free Transient Execution. - Michael Schwarz 001; Robert Schilling; Florian Kargl; Moritz Lipp; Claudio Canella; Daniel Gruss (CoRR, 2019)

ConTExT: A Generic Approach for Mitigating Spectre. - Michael Schwarz 001; Moritz Lipp; Claudio Canella; Robert Schilling; Florian Kargl; Daniel Gruss (NDSS, 2020)

CrypTag: Thwarting Physical and Logical Memory Vulnerabilities using Cryptographically Colored Memory. - Pascal Nasahl; Robert Schilling; Mario Werner; Jan Hoogerbrugge; Marcel Medwed; Stefan Mangard (AsiaCCS, 2021)

HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment. - Pascal Nasahl; Robert Schilling; Mario Werner; Stefan Mangard (AsiaCCS, 2021)

Protecting Indirect Branches Against Fault Attacks Using ARM Pointer Authentication. - Pascal Nasahl; Robert Schilling; Stefan Mangard (HOST, 2021)

SecWalk: Protecting Page Table Walks Against Fault Attacks. - Robert Schilling; Pascal Nasahl; Stefan Weiglhofer; Stefan Mangard (HOST, 2021)

FIPAC: Thwarting Fault- and Software-Induced Control-Flow Attacks with ARM Pointer Authentication. - Robert Schilling; Pascal Nasahl; Stefan Mangard (COSADE, 2022)

SFP: Providing System Call Flow Protection against Software and Fault Attacks. - Robert Schilling; Pascal Nasahl; Martin Unterguggenberger; Stefan Mangard (HASP@MICRO, 2022)

Multi-Tag: A Hardware-Software Co-Design for Memory Safety based on Multi-Granular Memory Tagging. - Martin Unterguggenberger; David Schrammel; Pascal Nasahl; Robert Schilling; Lukas Lamster; Stefan Mangard (AsiaCCS, 2023)

SCFI: State Machine Control-Flow Hardening Against Fault Attacks. - Pascal Nasahl; Martin Unterguggenberger; Rishub Nagpal; Robert Schilling; David Schrammel; Stefan Mangard (DATE, 2023)

FAULTLESS: Flexible and Transparent Fault Protection for Superscalar RISC-V Processors. - Moritz Waser; David Schrammel; Robert Schilling; Stefan Mangard (DIMVA (2), 2025)