Performance Comparison and Optimization: Case Studies using BenchIT. - Robert Schöne; Guido Juckeland; Wolfgang E. Nagel; Stefan Pflüger; R. Wloch (PARCO, 2005)

Optimizing OpenMP Parallelized DGEMM Calls on SGI Altix 3700. - Daniel Hackenberg; Robert Schöne; Wolfgang E. Nagel; Stefan Pflüger (Euro-Par, 2006)

Analyzing Cache Bandwidth on the Intel Core 2 Architecture. - Robert Schöne; Wolfgang E. Nagel; Stefan Pflüger (PARCO, 2007)

The Chemomentum Data Services - A Flexible Solution for Data Handling in UNICORE. - Katharina Rasch; Robert Schöne; Vitaliy Ostropytskyy; Hartmut Mix; Mathilde Romberg (Euro-Par Workshops, 2008)

Memory Performance and Cache Coherency Effects on an Intel Nehalem Multiprocessor System. - Daniel Molka; Daniel Hackenberg; Robert Schöne; Matthias S. Müller (PACT, 2009)

The VampirTrace Plugin Counter Interface: Introduction and Examples. - Robert Schöne; Ronny Tschüter; Thomas Ilsche; Daniel Hackenberg (Euro-Par Workshops, 2010)

Characterizing the energy consumption of data transfers and arithmetic operations on x86-64 processors. - Daniel Molka; Daniel Hackenberg; Robert Schöne; Matthias S. Müller (Green Computing Conference, 2010)

Quantifying power consumption variations of HPC systems using SPEC MPI benchmarks. - Daniel Hackenberg; Robert Schöne; Daniel Molka; Matthias S. Müller; Andreas Knüpfer (Comput. Sci. Res. Dev., 2010)

Memory Performance and SPEC OpenMP Scalability on Quad-Socket x86_64 Systems. - Daniel Molka; Robert Schöne; Daniel Hackenberg; Matthias S. Müller (ICA3PP (1), 2011)

Simultaneous multithreading on x86_64 systems: an energy efficiency evaluation. - Robert Schöne; Daniel Hackenberg; Daniel Molka (HotPower@SOSP, 2011)

On-line analysis of hardware performance events for workload characterization and processor frequency scaling decisions. - Robert Schöne; Daniel Hackenberg (ICPE, 2011)

Memory Performance at Reduced CPU Clock Speeds: An Analysis of Current x86_64 Processors. - Robert Schöne; Daniel Hackenberg; Daniel Molka (HotPower, 2012)

Flexible workload generation for HPC cluster efficiency benchmarking. - Daniel Molka; Daniel Hackenberg; Robert Schöne; Timo Minartz; Wolfgang E. Nagel (Comput. Sci. Res. Dev., 2012)

Introducing FIRESTARTER: A processor stress test utility. - Daniel Hackenberg; Roland Oldenburg; Daniel Molka; Robert Schöne (IGCC, 2013)

Power measurement techniques on standard compute nodes: A quantitative comparison. - Daniel Hackenberg; Thomas Ilsche; Robert Schöne; Daniel Molka; Maik Schmidt; Wolfgang E. Nagel (ISPASS, 2013)

Potentials and Limitations for Energy Efficiency Auto-Tuning. - Robert Schöne; Andreas Knüpfer; Daniel Molka (PARCO, 2013)

Analysis of Parallel Applications on a High Performance-Low Energy Computer. - Florina M. Ciorba; Thomas Ilsche; Elke Franz 001; Stefan Pfennig; Christian Scheunert; Ulf Markwardt; Joseph Schuchart; Daniel Hackenberg; Robert Schöne; Andreas Knüpfer; Wolfgang E. Nagel; Eduard A. Jorswieck; et al. (Euro-Par Workshops (2), 2014)

Main memory and cache performance of intel sandy bridge and AMD bulldozer. - Daniel Molka; Daniel Hackenberg; Robert Schöne (MSPC@PLDI, 2014)

HDEEM: high definition energy efficiency monitoring. - Daniel Hackenberg; Thomas Ilsche; Joseph Schuchart; Robert Schöne; Wolfgang E. Nagel; Marc Simon; Yiannis Georgiou (E2SC@SC, 2014)

Integrating performance analysis and energy efficiency optimizations in a unified environment. - Robert Schöne; Daniel Molka (Comput. Sci. Res. Dev., 2014)

Tools and methods for measuring and tuning the energy efficiency of HPC systems. - Robert Schöne; Jan Treibig; Manuel F. Dolz; Carla Guillén; Carmen B. Navarrete; Michael Knobloch; Barry Rountree (Sci. Program., 2014)

Power measurements for compute nodes: Improving sampling rates, granularity and accuracy. - Thomas Ilsche; Daniel Hackenberg; Stefan Graul; Robert Schöne; Joseph Schuchart (IGSC, 2015)

Cache Coherence Protocol and Memory Performance of the Intel Haswell-EP Architecture. - Daniel Molka; Daniel Hackenberg; Robert Schöne; Wolfgang E. Nagel (ICPP, 2015)

An Energy Efficiency Feature Survey of the Intel Haswell Processor. - Daniel Hackenberg; Robert Schöne; Thomas Ilsche; Daniel Molka; Joseph Schuchart; Robin Geyer 001 (IPDPS Workshops, 2015)

Wake-up latencies for processor idle states on current x86 processors. - Robert Schöne; Daniel Molka; Michael Werner (Comput. Sci. Res. Dev., 2015)

Software Controlled Clock Modulation for Energy Efficiency Optimization on Intel Processors. - Robert Schöne; Thomas Ilsche; Mario Bielert; Daniel Molka; Daniel Hackenberg (E2SC@SC, 2016)

The shift from processor power consumption to performance variations: fundamental implications at scale. - Joseph Schuchart; Daniel Hackenberg; Robert Schöne; Thomas Ilsche; Ramkumar Nagappan; Michael K. Patterson (Comput. Sci. Res. Dev., 2016)

lo2s - Multi-core System and Application Performance Analysis for Linux. - Thomas Ilsche; Robert Schöne; Mario Bielert; Andreas Gocht; Daniel Hackenberg (CLUSTER, 2017)

Powernightmares: The Challenge of Efficiently Using Sleep States on Multi-core Systems. - Thomas Ilsche; Marcus Hähnel; Robert Schöne; Mario Bielert; Daniel Hackenberg (Euro-Par Workshops, 2017)

Towards fine-grained dynamic tuning of HPC applications on modern multi-core architectures. - Mohammed Sourouri; Espen Birger Raknes; Nico Reissmann; Johannes Langguth; Daniel Hackenberg; Robert Schöne; Per Gunnar Kjeldsberg (SC, 2017)

Detecting Memory-Boundedness with Hardware Performance Counters. - Daniel Molka; Robert Schöne; Daniel Hackenberg; Wolfgang E. Nagel (ICPE, 2017)

A Unified Infrastructure for Monitoring and Tuning the Energy Efficiency of HPC Applications. - Robert Schöne (2017)

System Monitoring with lo2s: Power and Runtime Impact of C-State Transitions. - Thomas Ilsche; Robert Schöne; Philipp Joram; Mario Bielert; Andreas Gocht (IPDPS Workshops, 2018)

A New Approach for Automated Feature Selection. - Andreas Gocht; Christoph Lehmann; Robert Schöne (GI-Jahrestagung, 2019)

Q-Learning Inspired Self-Tuning for Energy Efficiency in HPC. - Andreas Gocht; Robert Schöne; Mario Bielert (HPCS, 2019)

Energy Efficiency Features of the Intel Skylake-SP Processor and Their Impact on Performance. - Robert Schöne; Thomas Ilsche; Mario Bielert; Andreas Gocht; Daniel Hackenberg (HPCS, 2019)

MetricQ: A Scalable Infrastructure for Processing High-Resolution Time Series Data. - Thomas Ilsche; Daniel Hackenberg; Robert Schöne; Mario Höpfner; Wolfgang E. Nagel (DAAC@SC, 2019)

Power measurement techniques for energy-efficient computing: reconciling scalability, resolution, and accuracy. - Thomas Ilsche; Robert Schöne; Joseph Schuchart; Daniel Hackenberg; Marc Simon; Yiannis Georgiou; Wolfgang E. Nagel (SICS Softw.-Intensive Cyber Phys. Syst., 2019)

Advanced Python Performance Monitoring with Score-P. - Andreas Gocht; Robert Schöne; Jan Frenzel (CoRR, 2020)

Energy Efficiency Aspects of the AMD Zen 2 Architecture. - Robert Schöne; Thomas Ilsche; Mario Bielert; Markus Velten; Markus Schmidl; Daniel Hackenberg (CLUSTER, 2021)

FIRESTARTER 2: Dynamic Code Generation for Processor Stress Tests. - Robert Schöne; Markus Schmidl; Mario Bielert; Daniel Hackenberg (CLUSTER, 2021)

Controlling the Runtime Overhead of Python Monitoring with Selective Instrumentation. - Andreas Gocht; Alexander Grund; Robert Schöne (ProTools@SC, 2021)

Investigating the Cause and Effect of an AMD Zen Energy Management Anomaly. - Christian von Elm; Thomas Ilsche; Robert Schöne; Mario Bielert; Markus Schmidl (ICPE (Companion), 2021)

Memory Performance of AMD EPYC Rome and Intel Cascade Lake SP Server Processors. - Markus Velten; Robert Schöne; Thomas Ilsche; Daniel Hackenberg (ICPE, 2022)

How Do OS and Application Schedulers Interact? An Investigation with Multithreaded Applications. - Jonas H. Müller Korndörfer; Ahmed Eleliemy; Osman Seckin Simsek; Thomas Ilsche; Robert Schöne; Florina M. Ciorba (Euro-Par, 2023)

Optimizing Idle Power of HPC Systems: Practical Insights and Methods. - Thomas Ilsche; Sebastian Schräder; Robert Schöne (CLUSTER Workshops, 2024)

16 Years of SPEC Power: An Analysis of x86 Energy Efficiency Trends. - Hannes Tröpgen; Robert Schöne; Thomas Ilsche; Daniel Hackenberg (CLUSTER Workshops, 2024)

Towards Large-Scale Top-Down Microarchitecture Analysis Using the Score-P Framework. - Maximilian Sander; Hannes Tröpgen; Christian von Elm; Robert Schöne (Euro-Par Workshops (1), 2024)

Introducing the Arm-Membench Throughput Benchmark. - Cyrill Burth; Markus Velten; Robert Schöne (PPAM (1), 2024)

Energy Efficiency Features of the Intel Alder Lake Architecture. - Robert Schöne; Markus Velten; Daniel Hackenberg; Thomas Ilsche (ICPE, 2024)

Performance Tools for the NEC SX-Aurora Tsubasa. - Christian von Elm; Robert Schöne (ICPE (Companion), 2025)

An Analysis of User-space Idle State Instructions on x86 Processors. - Malte-Christian Kuns; Hannes Tröpgen; Robert Schöne (ICPE, 2025)