A 14-bit 125 MS/s IF/RF sampling pipelined A/D converter. - Ahmed M. A. Ali; Christopher Dillon; Robert Sneed; Andrew S. Morgan; John Kornblum; Lu Wu; Scott Bardsley (CICC, 2005)

A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter. - Ahmed M. A. Ali; Christopher Dillon; Robert Sneed; Andrew S. Morgan; Scott Bardsley; John Kornblum; Lu Wu (IEEE J. Solid State Circuits, 2006)

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration. - Ahmed M. A. Ali; Andy Morgan; Christopher Dillon; Greg Patterson; Scott Puckett; Mike Hensley; Russell Stop; Paritosh Bhoraskar; Scott Bardsley; David Lattimore; Jeff Bray; Carroll Speir; et al. (ISSCC, 2010)

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration. - Ahmed M. A. Ali; Andrew S. Morgan; Christopher Dillon; Greg Patterson; Scott Puckett; Paritosh Bhoraskar; Hüseyin Dinc; Mike Hensley; Russell Stop; Scott Bardsley; David Lattimore; Jeff Bray; et al. (IEEE J. Solid State Circuits, 2010)