The Design of an Asynchronous MIPS R3000 Microprocessor. - Alain J. Martin; Andrew Lines; Rajit Manohar; Mika Nyström; Paul I. Pénzes; Robert Southworth; Uri Cummings (ARVLSI, 1997)

A 72-Port 10G Ethernet Switch/Router Using Quasi-Delay-Insensitive Asynchronous Design. - Mike Davies 002; Andrew Lines; Jon Dama; Alain Gravel; Robert Southworth; Georgios D. Dimou; Peter A. Beerel (ASYNC, 2014)