Reducing FPGA Memory Footprint of Stencil Codes through Automatic Extraction of Memory Patterns. - Robert Szafarczyk; Syed Waqar Nabi; Wim Vanderbauwhede (FPL, 2022)

Dynamically Scheduled Memory Operations in Static High-Level Synthesis. - Robert Szafarczyk; Syed Waqar Nabi; Wim Vanderbauwhede (FCCM, 2023)

Compiler Discovered Dynamic Scheduling of Irregular Code in High-Level Synthesis. - Robert Szafarczyk; Syed Waqar Nabi; Wim Vanderbauwhede (FPL, 2023)

A High-Frequency Load-Store Queue with Speculative Allocations for High-Level Synthesis. - Robert Szafarczyk; Syed Waqar Nabi; Wim Vanderbauwhede (ICFPT, 2023)

Compiler Support for Speculation in Decoupled Access/Execute Architectures. - Robert Szafarczyk; Syed Waqar Nabi; Wim Vanderbauwhede (CC, 2025)

Dynamic Loop Fusion in High-Level Synthesis. - Robert Szafarczyk; Syed Waqar Nabi; Wim Vanderbauwhede (FPGA, 2025)