POWER2 instruction cache unit. - Jama Barreh; Robert T. Golla; L. Baba Arimilli; Paul J. Jordan (IBM J. Res. Dev., 1994)

Throughput-Oriented Multicore Processors. - James Laudon; Robert T. Golla; Greg Grohoski (Multicore Processors and Systems, 2009)

T4: A highly threaded server-on-a-chip with native support for heterogeneous computing. - Robert T. Golla; Paul J. Jordan (Hot Chips Symposium, 2011)

The next-generation 64b SPARC core in a T4 SoC processor. - Jinuk Luke Shin; Heechoul Park; Hongping Penny Li; Alan P. Smith 002; Youngmoon Choi; Harikaran Sathianathan; Sudesna Dash; Sebastian Turullols; Song Kim; Robert P. Masleid; Georgios K. Konstadinidis; Robert T. Golla; et al. (ISSCC, 2012)

Sparc T4: A Dynamically Threaded Server-on-a-Chip. - Manish K. Shah; Robert T. Golla; Greg Grohoski; Paul J. Jordan; Jama Barreh; Jeffrey Brooks; Mark Greenberg; Gideon Levinsky; Mark Luttrell; Christopher Olson; Zeid Samoail; Matt Smittle; et al. (IEEE Micro, 2012)

The Next Generation 64b SPARC Core in a T4 SoC Processor. - Jinuk Luke Shin; Robert T. Golla; Hongping Penny Li; Sudesna Dash; Youngmoon Choi; Alan P. Smith 002; Harikaran Sathianathan; Mayur Joshi; Heechoul Park; Mohamed Elgebaly; Sebastian Turullols; Song Kim; et al. (IEEE J. Solid State Circuits, 2013)

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. - Georgios K. Konstadinidis; Hongping Penny Li; Francis Schumacher; Venkatram Krishnaswamy; Hoyeol Cho; Sudesna Dash; Robert P. Masleid; Chaoyang Zheng; Yuanjung David Lin; Paul Loewenstein; Heechoul Park; Vijay Srinivasan; et al. (IEEE J. Solid State Circuits, 2016)