Voltage droop reduction using throttling controlled by timing margin feedback. - Michael S. Floyd; Alan J. Drake; Robert W. Berry; Harold Chase; Richard L. Willaman; Jarom Peña (VLSIC, 2012)

Runtime power reduction capability of the IBM POWER7+ chip. - Michael S. Floyd; Alan J. Drake; Nicole S. Schwartz; Robert W. Berry; Charles Lefurgy; Malcolm S. Ware; Karthick Rajamani; Victor V. Zyuban; Richard L. Willaman; Ruby M. Zgabay (IBM J. Res. Dev., 2013)

Active Guardband Management in Power7+ to Save Energy and Maintain Reliability. - Charles Lefurgy; Alan J. Drake; Michael S. Floyd; Malcolm Allen-Ware; Bishop Brock; José A. Tierno; John B. Carter; Robert W. Berry (IEEE Micro, 2013)