A 0.6V Programmable Frequency Divider and Digitally Controlled Oscillator for use in a Digital PLL in the Subthreshold Region. - Roberto Andrino Robles; Tomochika Harada (ICECS, 2020)

Evaluation of a Filter-less AD-PLL with a Wide Input Frequency Range Using a Fast-Locking Algorithm. - Roberto Andrino Robles; Tomochika Harada; Michio Yokoyama (ICECS, 2021)

A Low Power 0.6V Filter-less AD-PLL with a Fast Locking Algorithm in the Subthreshold Region. - Roberto Andrino Robles; Tomochika Harada (ISPACS, 2021)

A 0.6V Beat-Frequency ADC with Processing of Oscillator Internal States for Resolution Improvement. - Roberto Andrino Robles; Tomochika Harada (ICECS, 2023)

Internal-states beat-frequency ADC using a subcircuit sharing architecture for SNDR improvement with decreased area tradeoff. - Roberto Andrino Robles; Tomochika Harada (IEICE Electron. Express, 2024)