Test considerations for jitter tolerance of wireline receivers. - Roberto DiCecco; Roman Pahuta; Chris D. Holdenried; Saman Sadr (CCECE, 2014)

Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks. - Roberto DiCecco; Griffin Lacey; Jasmina Vasiljevic; Paul Chow; Graham W. Taylor; Shawki Areibi (FPT, 2016)

FPGA-based training of convolutional neural networks with a reduced precision floating-point library. - Roberto DiCecco; Lin Sun; Paul Chow (FPT, 2017)

DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration. - Mohamed S. Abdelfattah; David Han; Andrew Bitar; Roberto DiCecco; Shane O'Connell; Nitika Shanker; Joseph Chu; Ian Prins; Joshua Fender; Andrew C. Ling; Gordon R. Chiu (FPL, 2018)

Harnessing Numerical Flexibility for Deep Learning on FPGAs. - Andrew C. Ling; Mohamed S. Abdelfattah; Shane O'Connell; Andrew Bitar; David Han; Roberto DiCecco; Suchit Subhaschandra; Chris N. Johnson; Dmitry Denisenko; Joshua Fender; Gordon R. Chiu (HEART, 2018)

A software-defined tensor streaming multiprocessor for large-scale machine learning. - Dennis Abts; Garrin Kimmell; Andrew C. Ling; John Kim 001; Matthew Boyd; Andrew Bitar; Sahil Parmar; Ibrahim Ahmed 007; Roberto DiCecco; David Han; John Thompson; Michael Bye; et al. (ISCA, 2022)