A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors. - Roberto Giorgi; Cosimo Antonio Prete; Luigi M. Ricciardi; Gianpaolo Prina (EUROMICRO, 1996)

A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors. - Roberto Giorgi; Cosimo Antonio Prete; Gianpaolo Prina; Luigi M. Ricciardi (HICSS (1), 1997)

Cache memory design for embedded systems based on program locality analysis. - Roberto Giorgi; Cosimo Antonio Prete; Gianpaolo Prina (MSE, 1997)

Trace Factory: generating workloads for trace-driven simulation of shared-bus multiprocessors. - Roberto Giorgi; Cosimo Antonio Prete; Gianpaolo Prina; Luigi M. Ricciardi (IEEE Concurrency, 1997)

Analysis of Sharing Overhead in Shared Memory Multiprocessors. - Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (HICSS (7), 1998)

An educational environment for designing and performance tuning of embedded systems. - Roberto Giorgi; Cosimo Antonio Prete (WCAE@ISCA, 1998)

Process Migration Effects on Memory Performance of Multiprocessor. - Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (HiPC, 1999)

PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors. - Roberto Giorgi; Cosimo Antonio Prete (IEEE Trans. Parallel Distributed Syst., 1999)

Performance Analysis of Electronic Commerce Multiprocessor Server. - Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (HICSS, 2000)

Execution and Cache Performance of the Scheduled Dataflow Architecture. - Krishna M. Kavi; Joseph Arul; Roberto Giorgi (J. Univers. Comput. Sci., 2000)

Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications. - Krishna M. Kavi; Joseph Arul; Roberto Giorgi (PDCS, 2001)

Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload. - Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (HICSS, 2001)

Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. - Sandro Bartolini; Roberto Giorgi; Jelica Protic; Cosimo Antonio Prete; Mateo Valero (SIGARCH Comput. Archit. News, 2001)

Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. - Krishna M. Kavi; Roberto Giorgi; Joseph Arul (IEEE Trans. Computers, 2001)

Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture. - Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (NETWORKING Workshops, 2002)

Web-based training on computer architecture: the case for JCachesim. - Irina Branovic; Roberto Giorgi; Cosimo Antonio Prete (WCAE, 2002)

A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. - Sandro Bartolini; Irina Branovic; Roberto Giorgi; Enrico Martinelli (SBAC-PAD, 2004)

WebMIPS: a new web-based MIPS simulation environment for computer architecture education. - Irina Branovic; Roberto Giorgi; Enrico Martinelli (WCAE, 2004)

Speeding-up multiprocessors running DBMS workloads through coherence protocols. - Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (Int. J. High Perform. Comput. Netw., 2004)

A workload characterization of elliptic curve cryptography methods in embedded environments. - Irina Branovic; Roberto Giorgi; Enrico Martinelli (SIGARCH Comput. Archit. News, 2004)

Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload. - Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (J. Parallel Distributed Comput., 2005)

Issues in Embedded Single-Chip Multicore Architectures. - Sandro Bartolini; Roberto Giorgi (J. Embed. Comput., 2006)

Memory performance: dealing with applications, systems and architecture. - Sandro Bartolini; Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (SIGARCH Comput. Archit. News, 2006)

Reducing leakage in power-saving capable caches for embedded systems by using a filter cache. - Roberto Giorgi; Paolo Bennati (MEDEA@PACT, 2007)

DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. - Roberto Giorgi; Zdravko Popovic; Nikola Puzovic (SBAC-PAD, 2007)

Reducing Leakage through Filter Cache. - Roberto Giorgi; Paolo Bennati (DSD, 2008)

Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. - Roberto Giorgi; Zdravko Popovic; Nikola Puzovic; Arnaldo Azevedo; Ben H. H. Juurlink (DSD, 2008)

Filtering drowsy instruction cache to achieve better efficiency. - Roberto Giorgi; Paolo Bennati (SAC, 2008)

Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m). - Sandro Bartolini; Irina Branovic; Roberto Giorgi; Enrico Martinelli (IEEE Trans. Computers, 2008)

Instruction Set Extensions for Cryptographic Applications. - Sandro Bartolini; Roberto Giorgi; Enrico Martinelli (Cryptographic Engineering, 2009)

Introducing Hardware TLP Support in the Cell Processor. - Roberto Giorgi; Zdravko Popovic; Nikola Puzovic (CISIS, 2009)

Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture. - Roberto Giorgi; Zdravko Popovic; Nikola Puzovic (IPDPS, 2009)

Programming Abstractions and Toolchain for Dataflow Multithreading Architectures. - Kyriakos Stavrou; Demos Pavlou; Marios Nikolaides; Panayiotis Petrides; Paraskevas Evripidou; Pedro Trancoso; Zdravko Popovic; Roberto Giorgi (ISPDC, 2009)

Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture. - Roberto Giorgi; Zdravko Popovic; Nikola Puzovic (SAMOS, 2009)

Exploiting locality to improve leakage reduction in embedded drowsy I-caches at same area/speed. - Massimo Alioto; Paolo Bennati; Roberto Giorgi (ISCAS, 2010)

TERAFLUX: Exploiting Tera-device Computing Challenges. - Antoni Portero; Zhibin Yu; Roberto Giorgi (FET, 2011)

Embedded reconfigurable architectures. - Stephan Wong; Luigi Carro; Stamatios Kavvadias; Georgios Keramidas; Francesco Papariello; Claudio Scordino; Roberto Giorgi; Stefanos Kaxiras (CASES, 2012)

TERAFLUX: exploiting dataflow parallelism in teradevices. - Roberto Giorgi (Conf. Computing Frontiers, 2012)

Simulating the future kilo-x86-64 core processors and their infrastructure. - Antoni Portero; Alberto Scionti; Zhibin Yu; Paolo Faraboschi; Caroline Concatto; Luigi Carro; Arne Garbade; Sebastian Weis; Theo Ungerer; Roberto Giorgi (SpringSim (ANSS), 2012)

The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. - Marco Solinas; Rosa M. Badia; François Bodin; Albert Cohen 001; Paraskevas Evripidou; Paolo Faraboschi; Bernhard Fechner; Guang R. Gao; Arne Garbade; Sylvain Girbal; Daniel Goodman 001; Behram Khan; et al. (DSD, 2013)

Integration of simulators in virtual 3D computer science classroom. - Irina Branovic; Ranko Popovic; Nenad Jovanovic; Roberto Giorgi; Bosko Nikolic; Miodrag Zivkovic (EDUCON, 2014)

Dynamic power reduction in self-adaptive embedded systems through benchmark analysis. - Alberto Scionti; Stamatios Kavvadias; Roberto Giorgi (MECO, 2014)

An Introduction to DF-Threads and their Execution Model. - Roberto Giorgi; Paolo Faraboschi (SBAC-PAD (Workshops), 2014)

TERAFLUX: Harnessing dataflow in next generation teradevices. - Roberto Giorgi; Rosa M. Badia; François Bodin; Albert Cohen 001; Paraskevas Evripidou; Paolo Faraboschi; Bernhard Fechner; Guang R. Gao; Arne Garbade; Rahulkumar Gayatri; Sylvain Girbal; Daniel Goodman 001; et al. (Microprocess. Microsystems, 2014)

Enhancing an x86_64 multi-core architecture with data-flow execution support. - Nam Ho; Andrea Mondelli; Alberto Scionti; Marco Solinas; Antoni Portero; Roberto Giorgi (Conf. Computing Frontiers, 2015)

A matrix multiplier case study for an evaluation of a configurable dataflow-machine. - Lorenzo Verdoscia; Roberto Vaccaro; Roberto Giorgi (Conf. Computing Frontiers, 2015)

The AXIOM Software Layers. - Carlos Álvarez 001; Eduard Ayguadé; Javier Bueno; Antonio Filgueras; Daniel Jiménez-González; Xavier Martorell; Nacho Navarro; Dimitris Theodoropoulos; Dionisios N. Pnevmatikatos; Davide Catani; Claudio Scordino; Paolo Gai; et al. (DSD, 2015)

Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. - Andrea Mondelli; Nam Ho; Alberto Scionti; Marco Solinas; Antoni Portero; Roberto Giorgi (DSD, 2015)

Scalable Embedded Systems: Towards the Convergence of High-Performance and Embedded Computing. - Roberto Giorgi (EUC, 2015)

A field experience for a vehicle recognition system using magnetic sensors. - Giovanni Burresi; Roberto Giorgi (MECO, 2015)

The AXIOM project (Agile, eXtensible, fast I/O Module). - Dimitris Theodoropoulos; Dionisios N. Pnevmatikatos; Carlos Álvarez 001; Eduard Ayguadé; Javier Bueno; Antonio Filgueras; Daniel Jiménez-González; Xavier Martorell; Nacho Navarro; Carlos Segura; Carles Fernández; David Oro; et al. (SAMOS, 2015)

A scalable thread scheduling co-processor based on data-flow principles. - Roberto Giorgi; Alberto Scionti (Future Gener. Comput. Syst., 2015)

Special Section on Terascale Computing. - Stefan Wesner; Lutz Schubert; Rosa M. Badia; Antonio Rubio 001; Pier Stanislao Paolucci; Roberto Giorgi (Future Gener. Comput. Syst., 2015)

Guide to DataFlow Supercomputing - Basic Concepts, Case Studies, and a Detailed Example - Veljko Milutinovic; Jakob Salom; Nemanja Trifunovic; Roberto Giorgi (Springer, 2015)

Exploring dataflow-based thread level parallelism in cyber-physical systems. - Roberto Giorgi (Conf. Computing Frontiers, 2016)

AXIOM: A Hardware-Software Platform for Cyber Physical Systems. - Somnath Mazumdar; Eduard Ayguadé; Nicola Bettin; Javier Bueno; Sara Ermini; Antonio Filgueras; Daniel Jiménez-González; Carlos Álvarez-Martínez; Xavier Martorell; Francesco Montefoschi; David Oro; Dionisios N. Pnevmatikatos; et al. (DSD, 2016)

Architectural Support for Fault Tolerance in a Teradevice Dataflow System. - Sebastian Weis; Arne Garbade; Bernhard Fechner; Avi Mendelson; Roberto Giorgi; Theo Ungerer (Int. J. Parallel Program., 2016)

Making IoT with UDOO. - Antonio Rizzo; Giovanni Burresi; Francesco Montefoschi; Maurizio Caporali; Roberto Giorgi (IxD&A, 2016)

Rapid prototyping IoT solutions based on Machine Learning. - Antonio Rizzo; Francesco Montefoschi; Maurizio Caporali; Antonio Gisondi; Giovanni Burresi; Roberto Giorgi (ECCE, 2017)

AXIOM: A 64-bit reconfigurable hardware/software platform for scalable embedded computing. - Roberto Giorgi (MECO, 2017)

Chapter Two - Exploring Future Many-Core Architectures: The TERAFLUX Evaluation Framework. - Roberto Giorgi (Adv. Comput., 2017)

The AXIOM platform for next-generation cyber physical systems. - Dimitris Theodoropoulos; Somnath Mazumdar; Eduard Ayguadé; Nicola Bettin; Javier Bueno; Sara Ermini; Antonio Filgueras; Daniel Jiménez-González; Carlos Álvarez-Martínez; Xavier Martorell; Francesco Montefoschi; David Oro; et al. (Microprocess. Microsystems, 2017)

Energy Efficiency Exploration on the ZYNQ Ultrascale+. - Roberto Giorgi; Farnam Khalili; Marco Procaccini (ICM, 2018)

Scalable embedded computing through reconfigurable hardware: Comparing DF-Threads, cilk, openmpi and jump. - Roberto Giorgi (Microprocess. Microsystems, 2018)

AXIOM: A Scalable, Efficient and Reconfigurable Embedded Platform. - Roberto Giorgi; Marco Procaccini; Farnam Khalili (DATE, 2019)

Bridging a Data-Flow Execution Model to a Lightweight Programming Model. - Roberto Giorgi; Marco Procaccini (HPCS, 2019)

An Iris+Voice Recognition System for a Smart Doorbell. - Roberto Giorgi; Nicola Bettin; Sara Ermini; Francesco Montefoschi; Antonio Rizzo (MECO, 2019)

Embedded Face Analysis for Smart Videosurveillance. - Roberto Giorgi; David Oro; Sara Ermini; Francesco Montefoschi; Antonio Rizzo (MECO, 2019)

A Data-Flow Methodology for Accelerating FFT. - Lorenzo Verdoscia; Amin Sahebi; Roberto Giorgi (MECO, 2019)

Analyzing the Impact of Operating System Activity of Different Linux Distributions in a Distributed Environment. - Roberto Giorgi; Marco Procaccini; Farnam Khalili (PDP, 2019)

A Design Space Exploration Tool Set for Future 1K-core High-Performance Computers. - Roberto Giorgi; Marco Procaccini; Farnam Khalili (RAPIDO, 2019)

WebRISC-V: a Web-Based Education-Oriented RISC-V Pipeline Simulation Environment. - Roberto Giorgi; Gianfranco Mariotti (WCAE@ISCA, 2019)

Translating Timing into an Architecture: The Synergy of COTSon and HLS (Domain Expertise - Designing a Computer Architecture via HLS). - Roberto Giorgi; Farnam Khalili; Marco Procaccini (Int. J. Reconfigurable Comput., 2019)

DRT: A Lightweight Runtime for Developing Benchmarks for a Dataflow Execution Model. - Roberto Giorgi; Marco Procaccini; Amin Sahebi (ARCS, 2021)

The Italian research on HPC key technologies across EuroHPC. - Marco Aldinucci; Giovanni Agosta; Antonio Andreini; Claudio Agostino Ardagna; Andrea Bartolini; Alessandro Cilardo; Biagio Cosenza; Marco Danelutto; Roberto Esposito; William Fornaciari; Roberto Giorgi; Davide Lengani; et al. (CF, 2021)

The AXIOM Project: IoT on Heterogeneous Embedded Platforms. - Antonio Filgueras; Miquel Vidal; Marc Mateu; Daniel Jiménez-González; Carlos Álvarez 001; Xavier Martorell; Eduard Ayguadé; Dimitrios Theodoropoulos; Dionisios N. Pnevmatikatos; Paolo Gai; Stefano Garzarella; David Oro; et al. (IEEE Des. Test, 2021)

Extending Performance and Reliability via Modular FPGA Clusters. - Roberto Giorgi (MECO, 2022)

WebRISC-V: A 32/64-bit RISC-V pipeline simulation tool. - Gianfranco Mariotti; Roberto Giorgi (SoftwareX, 2022)

Distributed large-scale graph processing on FPGAs. - Amin Sahebi; Marco Barbone; Marco Procaccini; Wayne Luk; Georgi Gaydadjiev; Roberto Giorgi (J. Big Data, 2023)

Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions. - Marco Procaccini; Amin Sahebi; Marco Barbone; Wayne Luk; Georgi Gaydadjiev; Roberto Giorgi (PARMA-DITAM, 2024)

DF-Threads: A Scalable and Efficient Execution Paradigm for Edge Computing and HPC. - Roberto Giorgi (BigHPC@itaDATA, 2024)

A survey of graph convolutional networks (GCNs) in FPGA-based accelerators. - Marco Procaccini; Amin Sahebi; Roberto Giorgi (J. Big Data, 2024)

Enhancing Traffic Prediction with Spatio-Temporal Deep Learning: A GCN-LSTM Hybrid Model. - Aditi Ghosh; Maurizio Giacobbe; Muhammad Tahir Rafiq; Antonio Puliafito; Roberto Giorgi (MECO, 2025)

Real-time Object Detection on FPGA-based Heterogeneous MPSoCs: A Preliminary Analysis of the Execution Bottlenecks. - Seyed Hani Hozhabr; Roberto Giorgi (MECO, 2025)

A Survey on Real-Time Object Detection on FPGAs. - Seyed Hani Hozhabr; Roberto Giorgi (IEEE Access, 2025)

HashGrid: An optimized architecture for accelerating graph computing on FPGAs. - Amin Sahebi; Marco Procaccini; Roberto Giorgi (Future Gener. Comput. Syst., 2025)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes. - Roberto Giorgi; Gianfranco Mariotti (CoRR, 2025)

FREESS: An Educational Simulator of a RISC-V-Inspired Superscalar Processor Based on Tomasulo's Algorithm. - Roberto Giorgi (CoRR, 2025)