A 200-MHz IF 11-bit fourth-order bandpass ΔΣ ADC in SiGe. - Roberto Maurino; Peter Mole (IEEE J. Solid State Circuits, 2000)

Multibit quadrature sigma-delta modulator with DEM scheme. - Roberto Maurino; Christos Papavassiliou (ISCAS (1), 2004)

A 10mW 81dB cascaded multibit quadrature ΣΔ ADC with a dynamic element matching scheme. - Roberto Maurino; Christos Papavassiliou (ESSCIRC, 2005)

Quadrature ΣΔ modulators with a dynamic element matching scheme. - Roberto Maurino; Christos Papavassiliou (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Subtractive dithering technique for delta-sigma modulator. - Zhichao Tan; Roberto Maurino; Robert Adams 001; Khiem Nguyen (ISCAS, 2017)

5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability. - Hanqing Wang 004; Gerard Mora-Puchalt; Colin Lyden; Roberto Maurino; Christian Birk (ISSCC, 2017)

A 19 nV/√Hz Noise 2-µ: V Offset 75-/micro;A Capacitive-Gain Amplifier With Switched-Capacitor ADC Driving Capability. - Hanqing Wang 004; Gerard Mora-Puchalt; Colin Lyden; Roberto Maurino; Christian Birk (IEEE J. Solid State Circuits, 2017)

A 6 $ mu$ W 95 dB SNDR Inverter Based $ Sigma Delta$ Modulator With Subtractive Dithering and SAR Quantizer. - Huajun Zhang 001; Zhichao Tan; Yi Zhang; Baozhen Chen; Roberto Maurino; Robert Adams 001; Khiem Nguyen (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 128ksps 120dB THD Low Noise Analog Front End. - Gerard Mora-Puchalt; Gabriel Banarie; Pawel Czapor; Adrian Sherry; Roberto Maurino; Jesús Bonache; Italo Medina (ESSCIRC, 2022)