Availability analysis for synchronous data-flow graphs in mixed-criticality systems. - Roberto Medina 001; Etienne Borde; Laurent Pautet (SIES, 2016)

Directed Acyclic Graph Scheduling for Mixed-Criticality Systems. - Roberto Medina 001; Etienne Borde; Laurent Pautet (Ada-Europe, 2017)

Availability enhancement and analysis for mixed-criticality systems on multi-core. - Roberto Medina 001; Etienne Borde; Laurent Pautet (DATE, 2018)

Scheduling Multi-periodic Mixed-Criticality DAGs on Multi-core Architectures. - Roberto Medina 001; Etienne Borde; Laurent Pautet (RTSS, 2018)

Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded Systems. - Roberto Medina 001; Liliana Cucu-Grosjean (RTSS, 2019)

Deployment of mixed criticality and data driven systems on multi-cores architectures. (Déploiement de systèmes à flots de données en criticité mixte pour architectures multi-coeurs). - Roberto Medina 001 (2019)

Generalized Mixed-Criticality Static Scheduling for Periodic Directed Acyclic Graphs on Multi-Core Processors. - Roberto Medina 001; Etienne Borde; Laurent Pautet (IEEE Trans. Computers, 2021)

The Last-Level-Cache Interference in Guest Performance: a Case-Study with Zephyr OS. - Marcelo Ruaro; Hadrien Barral; Matteo Bertolino; Rodrigo Cataldo; Roberto Medina 001; Mohamed Karaoui; Etienne Borde (DSD, 2023)