Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. - Roberto Nonis; Nicola Da Dalt; Pierpaolo Palestri; Luca Selmi (IEEE J. Solid State Circuits, 2005)

A Design Methodology for MOS Current-Mode Logic Frequency Dividers. - Roberto Nonis; Enzo Palumbo; Pierpaolo Palestri; Luca Selmi (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Modeling and design of low power integrated circuits for frequency synthesis in CMOS technology. - Roberto Nonis (2007)

Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. - Luca Bizjak; Nicola Da Dalt; Peter Thurner; Roberto Nonis; Pierpaolo Palestri; Luca Selmi (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS. - Werner Grollitsch; Roberto Nonis; Nicola Da Dalt (ISSCC, 2010)

A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators. - Michele Nocente; Donald Fontanelli; Pierpaolo Palestri; Roberto Nonis; David Esseni; Luca Selmi (Int. J. Circuit Theory Appl., 2010)

A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (ISSCC, 2013)

digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture. - Roberto Nonis; Werner Grollitsch; Thomas Santa; Dmytro Cherniak; Nicola Da Dalt (IEEE J. Solid State Circuits, 2013)

Low power digitally controlled delay insertion unit and 1% accuracy 100MHz oscillator for precise dead-time insertion in DC-DC converters. - Dmytro Cherniak; Michael Aichner; Roberto Nonis; Nicola Da Dalt (ESSCIRC, 2015)

Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall. - Andrea Cossettini; Andrea Cristofoli; Werner Grollitsch; Lino Alves; Roberto Nonis; Luca Della Ricca; Pierpaolo Palestri; Luca Selmi (RTSI, 2015)

Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Roberto Nonis; Pierpaolo Palestri (APCCAS, 2016)

A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS. - Werner Grollitsch; Roberto Nonis (ESSCIRC, 2016)

Session 10 overview: Advanced wireline transceivers and PLLs. - Jaeha Kim; Roberto Nonis (ISSCC, 2016)

Design of a transmitter for high-speed serial interfaces in automotive micro-controller. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Roberto Nonis; Pierpaolo Palestri (MIPRO, 2016)

Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars. - Dmytro Chemiak; Salvatore Levantino; Carlo Samori; Roberto Nonis (ISCAS, 2017)

F2: High-performance frequency generation for wireless and wireline systems. - Jiayoon Ru; Kohei Onizuka; Pavan Kumar Hanumolu; Roberto Nonis; Howard C. Luong; Jan Craninckx (ISSCC, 2017)

Low noise active loop filter for radar PLL applications. - Andrea Donno; Stefano D'Amico; Roberto Nonis; Peter Thurner (ICICDT, 2018)

Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Matteo Bassi; Roberto Nonis; Pierpaolo Palestri (ISCAS, 2018)

A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation. - Dmytro Cherniak; Luigi Grimaldi; Luca Bertulessi; Carlo Samori; Roberto Nonis; Salvatore Levantino (ISSCC, 2018)

Session 25 overview: Clock generation for high-speed links: Wireline subcommittee. - Roberto Nonis; Pavan Kumar Hanumolu; Frank O'Mahony (ISSCC, 2018)

A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation. - Dmytro Cherniak; Luigi Grimaldi; Luca Bertulessi; Roberto Nonis; Carlo Samori; Salvatore Levantino (IEEE J. Solid State Circuits, 2018)

Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. - Andrea Bandiziol; Werner Grollitsch; Giovanni Steffan; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique. - Dmytro Cherniak; Carlo Samori; Roberto Nonis; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

On the Optimal Operation Frequency to Minimize Phase Noise in Integrated Harmonic Oscillators. - Alessandro Franceschin; Fabio Padovan; Roberto Nonis; Andrea Bevilacqua (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers. - Dylan D'Ampolo; Andrea Bandiziol; Davide Menin; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (APCCAS, 2019)

A 19.5 GHz 28 nm CMOS Class-C VCO with Reduced 1/f Noise Upconversion. - Alessandro Franceschin; Pietro Andreani; Fabio Padovan; Matteo Bassi; Roberto Nonis; Andrea Bevilacqua (ESSCIRC, 2019)

A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. - Alessio Cortiula; Martino Dazzi; Mattia Marcon; Davide Menin; Marco Scapol; Andrea Bandiziol; Andrea Cristofoli; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (MIPRO, 2019)

Analysis of Spurs Impact in PLL-Based FMCW Radar Systems. - Luigi Grimaldi; Dmytro Cherniak; Werner Grollitsch; Roberto Nonis (ISCAS, 2020)

Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications. - Davide Menin; Andrea Bandiziol; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 1.6-V Tolerant Multiplexer Switch With 0.96-V Core Devices in 28-nm CMOS Technology. - Giuseppe E. Biccario; Oleg Vitrenko; Roberto Nonis; Stefano D'Amico (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. - Pierpaolo Palestri; Ahmed Elnaqib; Davide Menin; Klaid Shyti; Francesco Brandonisio; Andrea Bandiziol; Davide Rossi; Roberto Nonis (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces. - Alessio Cortiula; Davide Menin; Andrea Bandiziol; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 5-V Switch for Analog Multiplexers With 2.5-V Transistors in 28-nm CMOS Technology. - Giuseppe E. Biccario; Oleg Vitrenko; Roberto Nonis; Stefano D'Amico (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A -44dB PSRR Analog Nested Digital Low Dropout Regulator for SoC applications in CMOS 28nm. - Stefano Bonomi; Werner Grollitsch; Sie Boo Chiang; Roberto Nonis (ISCAS, 2025)