A versatile hardware architecture for a CFAR detector based on a linear insertion sorter. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (FPL, 2008)

A Versatile Linear Insertion Sorter Based on a FIFO Scheme. - Roberto Perez-Andrade; René Cumplido; Fernando Martin del Campo; Claudia Feregrino Uribe (ISVLSI, 2008)

Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. - Fernando Martin del Campo; René Cumplido; Roberto Perez-Andrade; Aldo G. Orozco-Lugo (ReConFig, 2008)

A System on a Programmable Chip Architecture for Data-Dependent Superimposed Training Channel Estimation. - Fernando Martin del Campo; René Cumplido; Roberto Perez-Andrade; Aldo G. Orozco-Lugo (Int. J. Reconfigurable Comput., 2009)

A versatile linear insertion sorter based on an FIFO scheme. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (Microelectron. J., 2009)

Towards a reconfigurable hardware architecture for implementing a LDPC module suitable for software radio systems. - René Cumplido; Juan M. Campos; Claudia Feregrino Uribe; Jose Roberto Perez-Andrade (Dynamically Reconfigurable Architectures, 2010)

A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter. - Roberto Perez-Andrade; René Cumplido; Claudia Feregrino Uribe; Fernando Martin del Campo (Digit. Signal Process., 2010)

On a Hybrid and General Control Scheme for Algorithms Represented as a Polytope. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido; Juan M. Campos (IPDPS Workshops, 2011)

Towards Symbolic Run-Time Reconfiguration in Tightly-Coupled Processor Arrays. - Srinivas Boppu; Frank Hannig; Jürgen Teich; Roberto Perez-Andrade (ReConFig, 2011)

A multi-cycle fixed point square root module for FPGAs. - Fernando Martin del Campo; Alicia Morales-Reyes; Roberto Perez-Andrade; René Cumplido; Aldo G. Orozco-Lugo; Claudia Feregrino (IEICE Electron. Express, 2012)

Processor arrays generation for matrix algorithms used in embedded platforms. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido; Juan M. Campos (ReConFig, 2013)

A parallelization methodology for reconfigurable systems applied to edge detection. - Juan M. Campos; René Cumplido; Claudia Feregrino Uribe; Roberto Perez-Andrade (ReCoSoC, 2013)

On an external memory scheme for processor arrays. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido; Juan M. Campos (IEICE Electron. Express, 2013)

Processor arrays generation for matrix algorithms used in embedded platforms implemented on FPGAs. - Roberto Perez-Andrade; César Torres-Huitzil; René Cumplido (Microprocess. Microsystems, 2015)