Digit On-line Large Radix CORDIC Rotator. - Roberto R. Osorio; Elisardo Antelo; Javier D. Bruguera; Julio Villalba; Emilio L. Zapata (ASAP, 1995)

New arithmetic coder/decoder architectures based on pipelining. - Roberto R. Osorio; Javier D. Bruguera (ASAP, 1997)

A VLSI implementation of an arithmetic coder for image compression. - Mercedes Peón; Roberto R. Osorio; Javier D. Bruguera (EUROMICRO, 1997)

Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory. - Roberto R. Osorio; Montserrat Bóo; Javier D. Bruguera (EUROMICRO, 1998)

New model for arithmetic coding/decoding of multilevel images based on a cache memory. - Roberto R. Osorio; Javier D. Bruguera (ICECS, 1999)

Architectures for arithmetic coding in image compression. - Roberto R. Osorio; Javier D. Bruguera (EUSIPCO, 2000)

Bitstream Syntax Description Language for 3D MPEG-4 view-dependent texture streaming. - Roberto R. Osorio; Sylvain Devillers; Eric Delfosse; Myriam Amielh; Gauthier Lafruit (ICIP (3), 2002)

High Speed 4-Symbol Arithmetic Encoder Architecture for Embedded Zero Tree-Based Compression. - Roberto R. Osorio; Bart Vanhoof (J. VLSI Signal Process., 2003)

Arithmetic Coding Architecture for H.264/AVC CABAC Compression System. - Roberto R. Osorio; Javier D. Bruguera (DSD, 2004)

View-dependent, scalable texture streaming in 3-D QoS with MPEG-4 visual texture coding. - Gauthier Lafruit; Eric Delfosse; Roberto R. Osorio; Wolfgang van Raemdonck; Vissarion Ferentinos (IEEE Trans. Circuits Syst. Video Technol., 2004)

A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder. - Roberto R. Osorio; Javier D. Bruguera (DSD, 2005)

A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. - Javier D. Bruguera; Roberto R. Osorio (DSD, 2006)

A Combined Memory Compression And Hierarchical Motion Estimation Architecture For Video Encoding In Embedded Systems. - Roberto R. Osorio; Javier D. Bruguera (DSD, 2006)

High-Throughput Architecture for H.264/AVC CABAC Compression System. - Roberto R. Osorio; Javier D. Bruguera (IEEE Trans. Circuits Syst. Video Technol., 2006)

Entropy Coding on a Programmable Processor Array for Multimedia SoC. - Roberto R. Osorio; Javier D. Bruguera (ASAP, 2007)

An FPGA architecture for CABAC decoding in manycore systems. - Roberto R. Osorio; Javier D. Bruguera (ASAP, 2008)

High Performance Image Processing on a Massively Parallel Processor Array. - Roberto R. Osorio; Cesar Diaz-Resco; Javier D. Bruguera (DSD, 2009)

A digital cellular-based system for retinal vessel-tree extraction. - Cesar Diaz-Resco; Alejandro Nieto; Roberto R. Osorio; Víctor M. Brea 001; David López Vilariño (ECCTD, 2009)

Performance analysis of massively parallel embedded hardware architectures for retinal image processing. - Alejandro Nieto; Víctor M. Brea 001; David López Vilariño; Roberto R. Osorio (EURASIP J. Image Video Process., 2011)

Fast Construction of Nearly-Optimal Prefix Codes without Probability Sorting. - Roberto R. Osorio; Patricia González (DCC, 2012)

Architecture and Implementation of a Data Compression System at Switch-Level in ATA-over-Ethernet Storage Networks. - Angela Souto Vieites; Roberto R. Osorio (DSD, 2013)

Improving Scalability of Application-Level Checkpoint-Recovery by Reducing Checkpoint Sizes. - Iván Cores; Gabriel Rodríguez 001; María J. Martín; Patricia González; Roberto R. Osorio (New Gener. Comput., 2013)

High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. - Roberto R. Osorio; Javier D. Bruguera (J. Signal Process. Syst., 2013)

Pipelined FPGA implementation of numerical integration of the Hodgkin-Huxley model. - Roberto R. Osorio (ASAP, 2016)

A fast algorithm for constructing nearly optimal prefix codes. - Roberto R. Osorio; Patricia González (Softw. Pract. Exp., 2016)

Hardware Implementation of Statecharts for FPGA-based Control in Scientific Facilities. - Javier Cereijo García; Roberto R. Osorio (DCIS, 2019)

A Microprogrammed Approach for Implementing Statecharts. - Javier Cereijo García; Roberto R. Osorio (DSD, 2019)

Truncated SIMD Multiplier Architecture for Approximate Computing in Low-Power Programmable Processors. - Roberto R. Osorio; Gabriel Rodríguez 001 (IEEE Access, 2019)

An efficient ant colony optimization framework for HPC environments. - Patricia González; Roberto R. Osorio; Xoán C. Pardo; Julio R. Banga; Ramón Doallo (Appl. Soft Comput., 2022)

Floating Point Calculation of the Cube Function on FPGAs. - Roberto R. Osorio (IEEE Trans. Parallel Distributed Syst., 2023)

Implementation of a motion estimation algorithm for Intel FPGAs using OpenCL. - Manuel de Castro; Roberto R. Osorio; David López Vilariño; Arturo González-Escribano; Diego R. Llanos (J. Supercomput., 2023)

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL. - Manuel de Castro; Roberto R. Osorio; Francisco J. Andújar; Rocío Carratalá-Sáez; Yuri Torres; Diego R. Llanos (Euro-Par Workshops (1), 2024)

Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools. - Manuel de Castro; Roberto R. Osorio; Francisco J. Andujar; Rocío Carratalá-Sáez; Yuri Torres; Diego R. Llanos (CoRR, 2024)

Challenging Portability Paradigms: FPGA Acceleration Using SYCL and OpenCL. - Manuel de Castro; Francisco J. Andújar; Roberto R. Osorio; Rocío Carratalá-Sáez; Diego R. Llanos (CoRR, 2024)

Accelerating Scientific Model Optimization with a Pipelined FPGA-Based Differential Evolution Engine. - Manuel de Castro; Roberto R. Osorio; Yuri Torres; Diego R. Llanos (FCCM, 2025)

Comparing Portability of FPGA High-Level Synthesis Frameworks in the Context of a Highly-Parallel Application. - Manuel de Castro; Roberto R. Osorio; Francisco J. Andújar; Rocío Carratalá-Sáez; Yuri Torres; Diego R. Llanos (IEEE Access, 2025)