Two-dimensional IC layout compaction based on topological design rule checking. - John Valainis; Sinan Kaptanoglu; Erwin Liu; Roberto Suaya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

From formal verification to silicon compilation. - Jeffrey Joyce; Erwin Liu; John M. Rushby; Natarajan Shankar; Roberto Suaya; Friedrich W. von Henke (Compcon, 1991)

A Two-Dimensional Topological Compactor With Octagonal Geometry. - Paul de Dood; John Wawrzynek; Erwin Liu; Roberto Suaya (DAC, 1991)

Transmission line design of clock trees. - Rafael Escovar; Roberto Suaya (ICCAD, 2002)

Mutual inductance extraction and the dipole approximation. - Rafael Escovar; Salvador Ortiz 002; Roberto Suaya (ISPD, 2004)

Optimal design of clock trees for multigigahertz applications. - Rafael Escovar; Roberto Suaya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies? - Chung-Kuan Cheng; Steve Lin; Andrew B. Kahng; Keh-Jeng Chang; Vijay Pitchumani; Toshiyuki Shibuya; Roberto Suaya; Zhiping Yu; Fook-Luen Heng; Don MacMillen (ASP-DAC, 2005)

An improved long distance treatment for mutual inductance. - Rafael Escovar; Salvador Ortiz 002; Roberto Suaya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Fullwave volumetric Maxwell solver using conduction modes. - Salvador Ortiz 002; Roberto Suaya (ICCAD, 2006)

Mutual inductance between intentional inductors: closed form expressions. - Rafael Escovar; Salvador Ortiz 002; Roberto Suaya (ISCAS, 2006)

Efficient implementation of conduction modes for modelling skin effect. - Salvador Ortiz 002; Roberto Suaya (ISVLSI, 2007)

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (DATE, 2008)

Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate. - Navin Srivastava; Roberto Suaya; Kaustav Banerjee (DATE, 2010)

Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060]. - Navin Srivastava; Chuan Xu; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

An efficient framework for passive compact dynamical modeling of multiport linear systems. - Zohaib Mahmood; Roberto Suaya; Luca Daniel (DATE, 2012)

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates. - Chuan Xu; Navin Srivastava; Roberto Suaya; Kaustav Banerjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm. - Shomit Das; Georgios Manetas; Kenneth S. Stevens; Roberto Suaya (NOCS, 2013)

Low Power SPI Design Based on Relative Timing Techniques. - Guillermo H. Makar; Francisco J. Badenas; Roberto G. Simone; Alejandro Furfaro; Kenneth S. Stevens; Roberto Suaya (ICECS, 2019)