Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques. - Elizabeth M. Rudnick; Roberto Vietti; Akilah Ellis; Fulvio Corno; Paolo Prinetto; Matteo Sonza Reorda (DATE, 1998)

A System for Evaluating On-Line Testability at the RT-level. - Silvia Chiusano; Fulvio Corno; Matteo Sonza Reorda; Roberto Vietti (DFT, 1998)

Enhancing topological ATPG with high-level information and symbolic techniques. - Fulvio Corno; Janak H. Patel; Elizabeth M. Rudnick; Matteo Sonza Reorda; Roberto Vietti (ICCD, 1998)