Developing a DSS for Allocating Gates to Flights at an International Airport. - Vincent F. Yu; Katta G. Murty; Yat-wah Wan; Jerry Dann; Robin Lee (Int. J. Decis. Support Syst. Technol., 2009)

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs. - Yen-Huei Chen; Gary Chan; Shao-Yu Chou; Hsien-Yu Pan; Jui-Jen Wu; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2009)

A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications. - Meng-Fan Chang; Jui-Jen Wu; Kuang-Ting Chen; Yung-Chi Chen; Yen-Hui Chen; Robin Lee; Hung-Jen Liao; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2010)

A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays. - Robin Lee; Jung-Ping Yang; Chia-En Huang; Chih-Chieh Chiu; Wei-Shuo Kao; Hong-Chen Cheng; Hong-Jen Liao; Jonathan Chang (VLSIC, 2012)

A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications. - Jonathan Chang; Yen-Huei Chen; Hank Cheng; Wei-Min Chan; Hung-Jen Liao; Quincy Li; Stanley Chang; Sreedhar Natarajan; Robin Lee; Ping-Wei Wang; Shyue-Shyh Lin; Chung-Cheng Wu; et al. (ISSCC, 2013)

A configurable 2-in-1 SRAM compiler with constant-negative-level write driver for low Vmin in 16nm Fin-FET CMOS. - Ching-Wei Wu; Ming-Hung Chang; Chia-Cheng Chen; Robin Lee; Hung-Jen Liao; Jonathan Chang (A-SSCC, 2014)

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. - Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Sahil Preet Singh; Hank Cheng; Hidehiro Fujiwara; Jih-Yu Lin; Kao-Cheng Lin; John Hung; Robin Lee; Hung-Jen Liao; Jhon-Jhy Liaw; et al. (ISSCC, 2017)

12.3 A low-power and high-performance 10nm SRAM architecture for mobile applications. - Michael Clinton; Hank Cheng; Hung-Jen Liao; Robin Lee; Ching-Wei Wu; Johnny Yang; Hau-Tai Hsieh; Frank Wu; Jung-Ping Yang; Atul Katoch; Arun Achyuthan; Donald Mikan; et al. (ISSCC, 2017)

Evaluation of Parallel Tempering to Accelerate Bayesian Parameter Estimation in Systems Biology. - Sanjana Gupta; Liam Hainsworth; Justin S. Hogg; Robin Lee; James R. Faeder (PDP, 2018)

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (ISSCC, 2020)

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; Wei-Min Chan; Hank Cheng; Po-Sheng Wang; Yangsyu Lin; Hidehiro Fujiwara; Robin Lee; Hung-Jen Liao; Ping-Wei Wang; Geoffrey Yeap; Quincy Li (IEEE J. Solid State Circuits, 2021)

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications. - Jonathan Chang; Yen-Huei Chen; Gary Chan; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Sevic Chen; Peijiun Lin; Ching-Wei Wu; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; et al. (VLSI Technology and Circuits, 2023)

A 38.1Mb/mm2 SRAM in a 2nm-CMOS-Nanosheet Technology for High-Density and Energy-Efficient Compute. - Tsung-Yung Jonathan Chang; Yen-Huei Chen; K. Venkateswara Reddy; Nikhil Puri; Teja Masina; Kuo-Cheng Lin; Po-Sheng Wang; Yangsyu Lin; Chih-Yu Lin; Yi-Hsin Nien; Hidehiro Fujiwara; Ku-Feng Lin; et al. (ISSCC, 2025)

An Efficient Algorithm for Generating Minimal Unique-Cause MC/DC Test cases for Singular Boolean Expressions. - Robin Lee; Youngho Nam (CoRR, 2025)