Implementing a 2-Gbs 1024-bit 1/2-rate low-density parity-check code decoder in three-dimensional integrated circuits. - Lili Zhou; Cherry Wakayama; Robin Panda; Nuttorn Jangkrajarng; Bo Hu; Chuanjin Richard Shi (ICCD, 2007)

Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays. - Brian Van Essen; Aaron Wood; Allan Carroll; Stephen Friedman; Robin Panda; Benjamin Ylvisaker; Carl Ebeling; Scott Hauck (FPL, 2009)

Managing Short-Lived and Long-Lived Values in Coarse-Grained Reconfigurable Arrays. - Brian Van Essen; Robin Panda; Aaron Wood; Carl Ebeling; Scott Hauck (FPL, 2010)

Software Managed Distributed Memories in MPPAs. - Robin Panda; Jimmy Xu; Scott Hauck (FPL, 2010)

Dynamic Communication in a Coarse Grained Reconfigurable Array. - Robin Panda; Scott Hauck (FCCM, 2011)

Energy-efficient specialization of functional units in a coarse-grained reconfigurable array. - Brian Van Essen; Robin Panda; Aaron Wood; Carl Ebeling; Scott Hauck (FPGA, 2011)

Dataflow-driven execution control in a coarse-grained reconfigurable array (abstract only). - Robin Panda; Scott Hauck (FPGA, 2012)

Adding dataflow-driven execution control to a Coarse-Grained Reconfigurable Array. - Robin Panda; Carl Ebeling; Scott Hauck (FPL, 2012)